參數(shù)資料
型號(hào): LPC2102FHN48,551
廠商: NXP Semiconductors
文件頁(yè)數(shù): 2/37頁(yè)
文件大小: 0K
描述: IC ARM7 MCU FLASH 16K 48-HVQFN
標(biāo)準(zhǔn)包裝: 260
系列: LPC2100
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 70MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.65 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-VFQFN 裸露焊盤
包裝: 托盤
配用: 568-4310-ND - EVAL BOARD LPC2158 W/LCD
568-4297-ND - BOARD EVAL LPC21XX MCB2100
MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME
MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2
622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K
其它名稱: 568-4689
935286982551
LPC2102FHN48-S
LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
10 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
6.
Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
The standard 32-bit ARM set.
A 16-bit Thumb set.
The Thumb set’s 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM’s performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular ash implementation in the LPC2101/02/03 allows for full speed execution
also in ARM mode. It is recommended to program performance critical and short code
sections in ARM mode. The impact on the overall code size will be minimal but the speed
can be increased by 30 % over Thumb mode.
6.2 On-chip ash program memory
The LPC2101/02/03 incorporate a 8 kB, 16 kB or 32 kB ash memory system
respectively. This memory may be used for both code and data storage. Programming of
the ash memory may be accomplished in several ways. It may be programmed in system
via the serial port. The application program may also erase and/or program the ash while
the application is running, allowing a great degree of exibility for data storage eld
rmware upgrades, etc. The entire ash memory is available for user code as the
bootloader resides in a separate memory.
The LPC2101/02/03 ash memory provides a minimum of 100,000 erase/write cycles and
20 years of data-retention memory.
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