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| 型號： | LPC2102FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7 MCU FLASH 16K 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs ARM7 Architecture ARM7 Memory |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | LPC2100 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 70MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 704 (CN2011-ZH PDF) |
| 配用： | 568-4310-ND - EVAL BOARD LPC2158 W/LCD 568-4297-ND - BOARD EVAL LPC21XX MCB2100 MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K |
| 其它名稱： | 568-2093 935280965151 LPC2102FBD48-S |
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LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
15 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
6.12 SSP serial I/O controller
The LPC2101/02/03 each contain one SSP. The SSP controller is capable of operation on
a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the
bus. However, only a single master and a single slave can communicate on the bus during
a given data transfer. The SSP supports full duplex transfers, with data frames of 4 bits to
16 bits owing from the master to the slave and from the slave to the master. Often only
one of these data streams carries meaningful data.
6.12.1 Features
Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor’s Microwire buses
Synchronous serial communication
Master or slave operation
8-frame FIFOs for both transmit and receive
Four bits to 16 bits per frame
6.13 General purpose 32-bit timers/external event counters
The Timer/Counter is designed to count cycles of the Peripheral Clock (PCLK) or an
externally supplied clock and optionally generate interrupts or perform other actions at
specied timer values, based on four match registers. It also includes four capture inputs
to trap the timer value when an input signal transitions, optionally generating an interrupt.
Multiple pins can be selected to perform a single capture or match function, providing an
application with ‘or’ and ‘a(chǎn)nd’, as well as ‘broadcast’ functions among them.
The LPC2101/02/03 can count external events on one of the capture inputs if the
minimum external pulse is equal or longer than a period of the PCLK. In this conguration,
unused capture lines can be selected as regular timer capture inputs or used as external
interrupts.
6.13.1 Features
A 32-bit timer/counter with a programmable 32-bit prescaler.
External event counter or timer operation.
Four 32-bit capture channels per timer/counter that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Four external outputs per timer/counter corresponding to match registers, with the
following capabilities:
– Set LOW on match.
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