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參數(shù)資料
| 型號： | LPC2102FBD48,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 11/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ARM7 MCU FLASH 16K 48-LQFP |
| 產(chǎn)品培訓模塊： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs ARM7 Architecture ARM7 Memory |
| 標準包裝： | 250 |
| 系列： | LPC2100 |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 70MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 16KB（16K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 4K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.65 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 704 (CN2011-ZH PDF) |
| 配用： | 568-4310-ND - EVAL BOARD LPC2158 W/LCD 568-4297-ND - BOARD EVAL LPC21XX MCB2100 MCB2103UME-ND - BOARD EVAL MCB2103 + ULINK-ME MCB2103U-ND - BOARD EVAL MCB2103 + ULINK2 622-1005-ND - USB IN-CIRCUIT PROG ARM7 LPC2K |
| 其它名稱： | 568-2093 935280965151 LPC2102FBD48-S |
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LPC2101_02_03_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 2 June 2009
19 of 37
NXP Semiconductors
LPC2101/02/03
Single-chip 16-bit/32-bit microcontrollers
6.17.4 Code security (Code Read Protection - CRP)
This feature of the LPC2101/02/03 allows user to enable different levels of security in the
system so that access to the on-chip ash and use of the JTAG and ISP can be restricted.
When needed, CRP is invoked by programming a specic pattern into a dedicated ash
location. IAP commands are not affected by the CRP.
Implemented in bootloader code version 2.21 are three levels of the Code Read
Protection:
1. CRP1 disables access to chip via the JTAG and allows partial ash update (excluding
ash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and ash eld updates are needed but all sectors cannot be erased.
2. CRP2 disables access to chip via the JTAG and only allows full ash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to chip via
the JTAG pins and the ISP. This mode effectively disables ISP override using P0.14
pin, too. It is up to the user’s application to provide (if needed) ash update
mechanism using IAP calls or call reinvoke ISP command to enable ash update via
UART0.
Remark: Parts LPC2101/02/03 Revision ‘-’ have CRP2 enabled only (bootloader code
version 2.2).
6.17.5 External interrupt inputs
The LPC2101/02/03 include up to three edge or level sensitive external interrupt inputs as
selectable pin functions. When the pins are combined, external events can be processed
as three independent interrupt signals. The external interrupt inputs can optionally be
used to wake-up the processor from Power-down mode and Deep power-down mode.
Additionally all 10 capture input pins can also be used as external interrupts without the
option to wake the device up from Power-down mode.
6.17.6 Memory mapping control
The memory mapping control alters the mapping of the interrupt vectors that appear
beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip
ash memory, or to the on-chip static RAM. This allows code running in different memory
spaces to have control of the interrupts.
6.17.7 Power control
The LPC2101/02/03 supports three reduced power modes: Idle mode, Power-down
mode, and Deep power-down mode.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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