參數(shù)資料
型號(hào): LPC11U12FHN33/201,
廠商: NXP Semiconductors
文件頁(yè)數(shù): 14/72頁(yè)
文件大?。?/td> 0K
描述: IC MCU 32BIT 16K 33HVQFN
產(chǎn)品培訓(xùn)模塊: Code Density for LPC11xx
標(biāo)準(zhǔn)包裝: 260
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 6K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤(pán)
包裝: 托盤(pán)
其它名稱(chēng): 568-8559
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
21 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.11.1 Features
The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
Easy to configure as master, slave, or master/slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes.
The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.12 10-bit ADC
The LPC11U1x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.12.1 Features
10-bit successive approximation ADC.
Input multiplexing among 8 pins.
Power-down mode.
Measurement range 0 V to VDD.
10-bit conversion time 2.44 s (up to 400 kSamples/s).
Burst conversion mode for single or multiple inputs.
Optional conversion on transition of input pin or timer match signal.
Individual result registers for each ADC channel to reduce interrupt overhead.
7.13 General purpose external event counter/timers
The LPC11U1x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.13.1 Features
A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
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