參數(shù)資料
型號: LPC11U12FBD48
廠商: NXP Semiconductors N.V.
元件分類: 32位微控制器
英文描述: 32-bit ARM Cortex-M0 microcontroller; up to 16 kB flash; 6 kB SRAM; USB device; USART; 2 SSPs
中文描述: 32位ARM的Cortex-M0微控制器;最大16kB閃存;6kB 靜態(tài)隨機存儲器;USB驅(qū)動;通用同步/異步串行接收/發(fā)送器;2個同步串行接口控制器
封裝: LPC11U12FBD48/201<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;
文件頁數(shù): 48/64頁
文件大小: 898K
代理商: LPC11U12FBD48
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Objective data sheet
Rev. 1 — 11 April 2011
48 of 64
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
10.6 SSP interface
[1]
T
cy(clk)
= (SSPCLKDIV
×
(1 + SCR)
×
CPSDVSR) / f
main
. The clock cycle time derived from the SPI bit rate T
cy(clk)
is a function of the
main clock frequency f
main
, the SSP peripheral clock divider (SSPCLKDIV), the SSP SCR parameter (specified in the SSP0CR0
register), and the SSP CPSDVSR parameter (specified in the SSP clock prescale register).
[2]
T
amb
=
40
°
C to 85
°
C.
T
cy(clk)
= 12
×
T
cy(PCLK)
.
T
amb
= 25
°
C; V
DD
= 3.3 V.
[3]
[4]
Table 16.
Symbol
SSP master
T
cy(clk)
Dynamic characteristics: SSP pins in SPI mode
Parameter
Conditions
Min
Max
Unit
clock cycle time
when only receiving
when only transmitting
in SPI mode;
2.4 V
V
DD
3.6 V
2.0 V
V
DD
< 2.4 V
in SPI mode
in SPI mode
in SPI mode
[1]
<tbd>
<tbd>
<tbd>
-
-
-
ns
ns
ns
[1]
t
DS
data set-up time
[2]
[2]
<tbd>
<tbd>
-
<tbd>
-
-
<tbd>
-
ns
ns
ns
ns
t
DH
t
v(Q)
t
h(Q)
SSP slave
T
cy(PCLK)
t
DS
t
DH
data hold time
data output valid time
data output hold time
[2]
[2]
[2]
PCLK cycle time
data set-up time
data hold time
<tbd>
<tbd>
<tbd>
×
T
cy(PCLK)
+
<tbd>
-
-
-
-
ns
ns
ns
in SPI mode
in SPI mode
[3][4]
[3][4]
t
v(Q)
data output valid time
in SPI mode
[3][4]
<tbd>
×
T
cy(PCLK)
+
<tbd>
<tbd>
×
T
cy(PCLK)
+
<tbd>
ns
t
h(Q)
data output hold time
in SPI mode
[3][4]
-
ns
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