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參數(shù)資料
| 型號(hào)： | LP87C54 |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM |
| 中文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 9/20頁(yè) |
| 文件大?。?/td> | 290K |
| 代理商： | LP87C54 |
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AUTOMOTIVE 87C54/87C54-20
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses to be superimposed on the V
OL
s of ALE and Ports 1, 2 and
3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0
transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the 0.9 V
CC
specification when the
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum V
CC
for Power Down is 2V.
4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
5V.
5. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin:
10mA
Maximum I
OL
per 8-bit portD
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total I
OL
for all output pins:
71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
270849–7
I
CC
Max at other frequencies is given by:
Active Mode
I
CC
Max
e
(1.25
c
Osc Freq)
a
8
Idle Mode
I
CC
Max
e
(0.5
c
Osc Freq)
a
4
Where Osc Freq is in MHz, I
CC
is in mA.
Figure 6. I
CC
vs Frequency
270849–8
All other pins disconnected
TCLCH
e
TCHCL
e
5 ns
Figure 7. I
CC
Test Condition, Active Mode
270849–9
All other pins disconnected
TCLCH
e
TCHCL
e
5 ns
Figure 8. I
CC
Test Condition Idle Mode
270849–10
All other pins disconnected
Figure 9. I
CC
Test Condition, Power Down Mode.
V
CC
e
2.0V to 6.0V.
270849–11
Figure 10. Clock Signal Waveform for I
CC
Tests in Active and Idle Modes. TCLCH
e
TCHCL
e
5 ns.
9
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