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參數(shù)資料
| 型號： | LP87C54-20 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH 16 KBYTES USER PROGRAMMABLE EPROM |
| 中文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 290K |
| 代理商： | LP87C54-20 |
AUTOMOTIVE 87C54/87C54-20
270849–5
C1, C2
e
30 pF
g
10 pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
Figure 4. Oscillator Connections
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 5. There are no requirements on the
duty cycle of the external clock signal, since the in-
put to the internal clocking circuitry is through a di-
vide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and V
IH
specifications the capacitance will not ex-
ceed 20 pF.
270849–6
Figure 5. External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consump-
tion is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated.
On the 87C54 either a hardware reset or an external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the on-
chip RAM. An external interrupt allows both the
SFRs and on-chip RAM to retain their values.
To properly terminate Power down the reset or ex-
ternal interrupt should not be executed before V
CC
is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt, INT0 or INT1 must be en-
abled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. (The oscillator must be
allowed time to stabilize after start up, before this pin
is released high.) Once the interrupt is serviced, the
next instruction to be executed after RETI will be the
one following the instruction that put the device into
Power Down.
DESIGN CONSIDERATION
When the idle mode is terminated by a hardware
reset, the device normally resumes program execu-
tion, from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-
chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To
eliminate the possibility of an unexpected write when
Idle is terminated by reset, the instruction following
the one that invokes Idle should not be one that
writes to a port pin or to external memory.
6
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