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參數(shù)資料
| 型號(hào)： | LP61L1008AS-8 |
| 廠商： | AMIC Technology Corporation |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM |
| 中文描述： | 128K的× 8位高速3.3V的中心功耗CMOS SRAM |
| 文件頁(yè)數(shù)： | 6/11頁(yè) |
| 文件大小： | 118K |
| 代理商： | LP61L1008AS-8 |
LP61L1008A
PRELIMINARY
(August, 2001, Version 1.0)
4
AMIC Technology, Inc.
Truth Table
Mode
CE
OE
WE
I/O Operation
Supply Current
Standby
H
X
High Z
ISB, ISB1
Output Disable
L
H
High Z
ICC1
Read
L
H
DOUT
ICC1
Write
L
X
L
DIN
ICC1
Note: X = H or L
Capacitance (TA = 25
°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
6
pF
VIN = 0V
CI/O*
Input/Output Capacitance
8
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0
°C to +70°C, VCC = 3.3V ± 10%, GND = 0V)
Symbol
Parameter
LP61L1008A-8
LP61L1008A-10
LP61L1008A-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
tRC
Read Cycle Time
8
-
10
-
12
-
ns
tAA
Address Access Time
-
8
-
10
-
12
ns
tACE
Chip Enable Access Time
CE
-
8
-
10
-
12
ns
tOE
Output Enable to Output Valid
-
4
-
5
-
6
ns
tCLZ
Chip Enable to Output in Low Z
CE
3
-
3
-
5
-
ns
tOLZ
Output Enable to Output in Low Z
0
-
0
-
2
-
ns
tCHZ
Chip Disable to Output in High Z
CE
-
4
-
5
-
6
ns
tOHZ
Output Disable to Output in High Z
0
4
0
5
2
6
ns
tOH
Output Hold from Address Change
3
-
3
-
5
-
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP61L1008S-12 | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM |
| LP61L1008S-15 | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM |
| LP61L1008X-12 | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM |
| LP61L1008X-15 | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM |
| LP61L1024 | 制造商:AMICC 制造商全稱(chēng):AMIC Technology 功能描述:128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM |
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