參數資料
型號: LP3945ILDX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: Battery Charge Management System
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
文件頁數: 5/15頁
文件大?。?/td> 337K
代理商: LP3945ILDX
Electrical Characteristics
(Continued)
Unless otherwise noted, V
= 5V, V
= 4V, C
= 1μF, C
= 10μF. Typical values and limits appearing in nor-
mal type apply for T
= 25C. Limits appearing in
boldface
type apply over the entire junction temperature range for operation,
T
J
= 40C to +85C. (Notes 6, 7, 8)
Symbol
Parameter
Conditions
Typical
Limit
Units
Min
Max
BATTERY CHARGER—Li ION MODE (MODE = LOW)
Restart Threshold Voltage
(For 4.1V Cell)
Restart Threshold Voltage
(For 4.2V Cell)
Internal Current Sense
Resistance
Internal Current Sense Resistor
Load Current
V
BAT-RST
V
BATT
Falling, Transition from
EOC, to Pre-Qualification State
V
BATT
Falling, Transition from
EOC, to Pre-Qualification State
3.9
3.77
4.02
V
4.00
3.86
4.12
R
SENSE
(Note 7)
120
m
(Note 7)
1.2
A
ICHG
MON
Diff-Amp Output
I
CHG
= 50 mA
I
CHG
= 500 mA
I
CHG
= 950 mA
0C to +85C (Note 7)
40C to +85C (Note 7)
0.583
1.333
2.090
5.625
5.625
V
t
EOC
Time to EOC State
4.78
4.5
6.42
6.75
Hrs
BATTERY CHARGER—NI-MH MODE (MODE = HIGH, LP3945 ONLY)
V
BATT-MAX
Battery Over Voltage Protection
(Charging Current Decreases to
0 mA when V
BATT
is above this
Voltage), V
CHG-IN
= 5.6V
5.4
5.292
5.508
V
LDO MODE (BIPB=HIGH)
V
OUT
Output Voltage Regulation
I
LOAD
=50mA
I
LOAD
=950mA
4.10
4.06
V
LOGIC LEVELS
V
IL
V
IH
Low Level Input Voltage
High Level Input Voltage
EN
EN
EN = LOW
EN = HIGH
0.4
V
V
2.0
10
5
I
IL
Enable Pin Input Current
+10
+5
μA
Electrical Characteristics, I
2
C Interface (LP3945 Only)
Unless otherwise noted, V
= 5V, V
= 4V. Typical values and limits appearing in normal type apply for T
= 25C.
Limits appearing in
boldface
type apply over the entire junction temperature range for operation, T
J
= 40C to +85C. (Notes
6, 7, 8)
Symbol
Parameter
Conditions
Typical
Limit
Units
Min
0.4
Max
0.3 V
DD
V
DD
+0.5
0.2 V
DD
V
IL
V
IH
V
OL
V
HYS
F
CLK
t
HOLD
Low Level Input Voltage
High Level Input Voltage
Low Level Output Voltage
Schmitt Trigger Input Hysteresis
Clock Frequency
Hold Time Repeated START
Condition
CLK Low Period
CLK High Period
Set-up Time Repeated START
Condition
Data Hold Time
Data Set-up Time
Set-up Time for STOP Condition
SDA & SCL
SDA & SCL
SDA & SCL
SDA & SCL
V
V
V
V
0.7 V
DD
0
0.1 V
DD
400
kHz
(Note 7)
0.6
μs
t
CLK-LP
t
CLK-HP
t
SU
(Note 7)
(Note 7)
(Note 7)
1.3
0.6
μs
μs
0.6
μs
t
DATA-HOLD
t
DATA-SU
t
SU
(Note 7)
(Note 7)
(Note 7)
300
100
0.6
ns
ns
μs
L
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