參數(shù)資料
型號: LP3927
廠商: National Semiconductor Corporation
英文描述: Cellular/PCS System Power Management IC
中文描述: 蜂窩/ PCS系統(tǒng)的電源管理IC
文件頁數(shù): 13/16頁
文件大小: 326K
代理商: LP3927
VEXT Detect W/Keyboard Interrupts
20037928
Note:
Diagram indicates Open Drain IRQ tied to V
DD
.
***
= Internal signal
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Delay between RST going low and LDO2 disabled.
11. Delay between LDO2 disable and LDO1 disabled.
VEXT goes active low.
VEXT 32 msec de-bounce period.
Delay between LDO1 and LDO2 enable.
Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start Reset timer.
Reset delay.
Keyboard de-bounce delay.
Keyboard pulse must be a minimum of 32 msec.
PS_HOLD may go low after Key press, but LDOs stay on since VEXT is low.
VEXT goes high, begin shutdown since PS_HOLD is low.
L
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