參數(shù)資料
型號: LP3927
廠商: National Semiconductor Corporation
英文描述: Cellular/PCS System Power Management IC
中文描述: 蜂窩/ PCS系統(tǒng)的電源管理IC
文件頁數(shù): 12/16頁
文件大小: 326K
代理商: LP3927
VEXT Detect Start-Up/Shut Down
20037927
Note:
Diagram indicates Open Drain IRQ tied to V
DD
.
***
= Internal signal
1.
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10. Delay between LDO2 and LDO1 disabled.
VEXT goes active low.
VEXT 32 msec de-bounce period.
Delay between LDO1 and LDO2 enables.
Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start Reset timer.
Reset delay.
Period between Reset and PS_HOLD going high is not relevant since VEXT is low
PS_HOLD goes low but LDOs continue to run since VEXT is low.
PS_HOLD is low and VEXT goes high, RST pin goes low.
Delay between RST going low and LDO2 disabled.
L
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