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參數(shù)資料
| 型號： | LP2995MX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | DDR Termination Regulator |
| 中文描述： | BUS TERMINATOR SUPPORT CIRCUIT, PDSO8 |
| 封裝： | SOP-8 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 291K |
| 代理商： | LP2995MX |
Pin Descriptions
AVIN AND PVIN
AVIN and PVIN are the input supply pins for the LP2995.
AVIN is used to supply all the internal control circuitry for the
two op-amps and the output stage of V
REF
. PVIN is used
exclusively to provide the rail voltage for the output stage on
the power operational amplifier used to create V
TT
. For
SSTL-2 applications AVIN and PVIN pins should be con-
nected directly and tied to the 2.5V rail for optimal perfor-
mance. This eliminates the need for bypassing the two sup-
ply pins separately.
VDDQ
VDDQ is the input that is used to create the internal refer-
ence voltage for regulating V
TT
and V
. This voltage is
generated by two internal 50k
resistors. This guarantees
that V
and V
will track VDDQ / 2 precisely. The optimal
implementation of VDDQ is as a remote sense for the refer-
ence input. This can be achieved by connecting VDDQ
directly to the 2.5V rail at the DIMM. This ensures that the
reference voltage tracks the DDR memory rails precisely
without a large voltage drop from the power lines. For
SSTL-2 applications VDDQ will be a 2.5V signal, which will
create a 1.25V reference voltage on V
and a 1.25V
termination voltage at V
. For SSTL-3 applications it may
be desirable to have a different scaling factor for creating the
internal reference voltage besides 0.5. For instance a typical
value that is commonly used is to have the reference voltage
equal VDDQ
*
0.45. This can be achieved by placing a resis-
tor in series with the VDDQ pin to effectively change the
resistor divider.
V
SENSE
The purpose of the sense pin is to provide improved remote
load regulation. In most motherboard applications the termi-
nation resistors will connect to V
TT
in a long plane. If the
output voltage was regulated only at the output of the
LP2995, then the long trace will cause a significant IR drop,
resulting in a termination voltage lower at one end of the bus
than the other. The V
pin can be used to improve this
performance, by connecting it to the middle of the bus. This
will provide a better distribution across the entire termination
bus.
Note:
If remote load regulation is not used, then the V
SENSE
pin must still be
connected to V
TT
.
V
REF
V
provides the buffered output of the internal reference
voltage VDDQ / 2. This output should be used to provide the
reference voltage for the Northbridge chipset and memory.
Since these inputs are typically an extremely high imped-
ance, there should be little current drawn from V
. For
improved performance, an output bypass capacitor can be
used, located close to the pin, to help with noise. A ceramic
capacitor in the range of 0.1 μF to 0.01 μF is recommended.
V
TT
V
TT
is the regulated output that is used to terminate the bus
resistors. It is capable of sinking and sourcing current while
regulating the output precisely to VDDQ / 2. The LP2995 is
designed to handle peak transient currents of up to
±
3Awith
a fast transient response. The maximum continuous current
is a function of V
IN
and can be viewed in the
TYPICAL
PERFORMANCE CHARACTERISTICS
section. If a tran-
sient is expected to last above the maximum continuous
current rating for a significant amount of time then the output
capacitor should be sized large enough to prevent an exces-
sive voltage drop. Despite the fact that the LP2995 is de-
signed to handle large transient output currents it is not
capable of handling these for long durations, under all con-
ditions. The reason for this is the standard packages are not
able to thermally dissipate the heat as a result of the internal
power loss. If large currents are required for longer dura-
tions, then care should be taken to ensure that the maximum
junction temperature is not exceeded. Proper thermal derat-
ing should always be used (please refer to the Thermal
Dissipation section).
Component Selection
INPUT CAPACITOR
The LP2995 does not require a capacitor for input stability,
but it is recommended for improved performance during
large load transients to prevent the input rail from dropping.
The input capacitor should be located as close as possible to
the PVIN pin. Several recommendations exist dependent on
the application required.Atypical value recommended forAL
electrolytic capacitors is 50 μF. Ceramic capacitors can also
be used, a value in the range of 10 μF with X5R or better
would be an ideal choice. The input capacitance can be
reduced if the LP2995 is placed close to the bulk capaci-
tance from the output of the 2.5V DC-DC converter.
OUTPUT CAPACITOr
The LP2995 has been designed to be insensitive of output
capacitor size or ESR (Equivalent Series Resistance). This
allows the flexibility to use any capacitor desired. The choice
for output capacitor will be determined solely on the applica-
tion and the requirements for load transient response of V
TT
.
As a general recommendation the output capacitor should
be sized above 100 μF with a low ESR for SSTL applications
with DDR-SDRAM. The value of ESR should be determined
by the maximum current spikes expected and the extent at
which the output voltage is allowed to droop. Several capaci-
tor options are available on the market and a few of these
are highlighted below:
AL - It should be noted that many aluminum electrolytics only
specify impedance at a frequency of 120 Hz, which indicates
they have poor high frequency performance. Only aluminum
electrolytics that have an impedance specified at a higher
frequency (between 20 kHz and 100 kHz) should be used for
the LP2995. To improve the ESR severalAL electrolytics can
be combined in parallel for an overall reduction.An important
note to be aware of is the extent at which the ESR will
change over temperature. Aluminum electrolytic capacitors
can have their ESR rapidly increase at cold temperatures.
Ceramic - Ceramic capacitors typically have a low capaci-
tance, in the range of 10 to 100 μF range, but they have
excellent AC performance for bypassing noise because of
very low ESR (typically less than 10 m
). However, some
dielectric types do not have good capacitance characteris-
tics as a function of voltage and temperature. Because of the
typically low value of capacitance it is recommended to use
ceramic capacitors in parallel with another capacitor such as
an aluminum electrolytic. A dielectric of X5R or better is
recommended for all ceramic capacitors.
Hybrid - Several hybrid capacitors such as OS-CON and SP
are available from several manufacturers. These offer a
large capacitance while maintaining a low ESR. These are
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP2995MX/J7001045 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LP2995MX/NOPB | 功能描述:低壓差穩(wěn)壓器 - LDO RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| LP2995MX-NOPB | 制造商:Texas Instruments 功能描述: |
| LP2996AMR/NOPB | 功能描述:DDR Terminator PMIC 8-SO PowerPad 制造商:texas instruments 系列:- 包裝:管件 零件狀態(tài):有效 應(yīng)用:DDR 端接器 電流 - 電源:320μA 電壓 - 電源:2.2 V ~ 5.5 V 工作溫度:0°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-PowerSOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:8-SO PowerPad 標(biāo)準(zhǔn)包裝:95 |
| LP2996AMRX/NOPB | 功能描述:DDR Terminator PMIC 8-SO PowerPad 制造商:texas instruments 系列:- 包裝:剪切帶（CT） 零件狀態(tài):有效 應(yīng)用:DDR 端接器 電流 - 電源:320μA 電壓 - 電源:2.2 V ~ 5.5 V 工作溫度:0°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-PowerSOIC（0.154"，3.90mm 寬） 供應(yīng)商器件封裝:8-SO PowerPad 標(biāo)準(zhǔn)包裝:1 |
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