參數(shù)資料
型號: LNBH221PD-TR
廠商: STMICROELECTRONICS
元件分類: 穩(wěn)壓器
英文描述: 0.75 A DUAL SWITCHING CONTROLLER, PDSO36
封裝: POWER, SO-36
文件頁數(shù): 3/29頁
文件大?。?/td> 800K
代理商: LNBH221PD-TR
LD39150
Application information
11/27
5.4
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
5.5
Acknowledge
The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7.). The peripheral (LNBH221) that acknowledges has to pull-down
(LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during this clock pulse. The peripheral which has been addressed has to generate an
acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH
level during the ninth clock pulse time. In this case the master transmitter can generate the
STOP information in order to abort the transfer. The LNBH221 won't generate the
acknowledge if the VCC supply is below the Undervoltage Lockout threshold (6.7V typ.).
5.6
Transmission without acknowledgement
Avoiding to detect the acknowledge of the LNBH221, the P can use a simpler
transmission: simply it waits one clock without checking the slave acknowledging, and
sends the new data.
This approach of course is less protected from misworking and decreases the noise
immunity..
Figure 5.
Data Validity On The I2C Bus
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