參數(shù)資料
型號(hào): LNBH221
廠商: 意法半導(dǎo)體
英文描述: DUAL LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE
中文描述: 雙LNB電源與控制集成電路升壓轉(zhuǎn)換器和I2C接口
文件頁數(shù): 6/18頁
文件大小: 515K
代理商: LNBH221
LNBH221
6/18
protected against overheating: when the junction temperature exceeds 150°C (typ.), the step-up
converter and the linear regulator are shut off, and the OTF SR bit is set to HIGH. Normal operation is
resumed and the OTF bit is reset to LOW when the junction is cooled down to 140°C (typ.).
(*): External components are needed to comply to bi-directional DiSEqC
TM
bus hardware requirements. Full compliance of the whole
application to DiSEqC
TM
specifications is not implied by the use of this IC.
NOTICE: DiSEqC is a trademark of EUTELSAT. I
C is a trademark of Philips Semiconductors.
I
2
C BUS INTERFACE
(one for each section)
Data transmission from main μP to the LNBH221 and viceversa takes place through the 2 wires I
2
C bus
interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH
and LOW state of the data line can only change when the clock signal on the SCL line is LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP conditions
must be sent before each START condition.
BYTE FORMAT
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
ACKNOWLEDGE
The master (μP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig.
3). The peripheral (LNBH221) that acknowledges has to pull-down (LOW) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The peripheral which
has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA
line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH221 won't generate the
acknowledge if the V
CC
supply is below the Undervoltage Lockout threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGEMENT
Avoiding to detect the acknowledge of the LNBH221, the μP can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking and decreases the noise immunity.
Figure 1 :
DATA VALIDITY ON THE I
2
C BUS
相關(guān)PDF資料
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