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參數(shù)資料
| 型號： | LNBH21PD-TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE |
| 中文描述： | LNB電源與控制集成電路升壓轉(zhuǎn)換器和I2C接口 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 493K |
| 代理商： | LNBH21PD-TR |
LNBH21
8/20
TRANSMITTED DATA (I
2
C BUS WRITE MODE)
When the R/W bit in the chip address is set to 0, the main μP can write on the System Register (SR) of the
LNBH21 via I
2
C bus. Only 6 bits out of the 8 available can be written by the μP, since the remaining 2 are
left to the diagnostic flags, and are read-only.
X= don't care.
Values are typical unless otherwise specified
RECEIVED DATA (I
2
C bus READ MODE)
The LNBH21 can provide to the Master a copy of the SYSTEM REGISTER information via I2C bus in read
mode. The read mode is Master activated by sending the chip address with R/W bit set to 1. At the
following master generated clocks bits, the LNBH21 issues a byte on the SDA data bus line (MSB
transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way the transmission of another byte from the LNBH21;
- no acknowledge, stopping the read mode communication.
While the whole register is read back by the μP, only the two read-only bits OLF and OTF convey
diagnostic informations about the LNBH21.
Values are typical unless otherwise specified.
Values are typical unless otherwise specified
POWER-ON I
2
C INTERFACE RESET
The I
2
C interface built in the LNBH21 is automatically reset at power-on. As long as the V
CC
stays below
the UnderVoltage Lockout threshold (6.7V typ.), the interface will not respond to any I
2
C command and
the System Register (SR) is initialized to all zeroes, thus keeping the power blocks disabled. Once the
V
CC
rises above 7.3V typ, the I
2
C interface becomes operative and the SR can be configured by the main
μP. This is due to 500mV of hysteresis provided in the UVL threshold to avoid false retriggering of the
Power-On reset circuit.
ADDRESS PIN
Connecting this pin to GND the Chip I
2
C interface address is 0001000, but, it is possible to choice among
4 different addresses simply setting this pin at 4 fixed voltage levels (see table on page 10).
PCL
TTX
TEN
LLC
VSEL
EN
OTF
OLF
Function
0
0
1
1
0
1
0
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
V
O
= 13.25 V, V
UP
= 15.25 V
V
O
= 18V, V
UP
=20 V
V
O
= 14.25 V, V
UP
= 16.25 V
V
O
= 19.5 V, V
UP
= 21.5 V
22KHz is controlled by DSQIN pin
22KHz tone is ON, DSQIN pin disabled
V
O
RX output is ON, output voltage controlled by VSEL and
LLC
V
O
TX output is ON, 22KHz controlled by DSQIN or TEN,
output voltage level controlled by VSEL and LLC
Pulsed (dynamic) current limiting is selected
Static current limiting is selected
Power blocks disabled
0
1
0
1
X
X
1
X
1
X
X
0
1
X
1
1
0
X
X
X
X
X
X
X
X
X
X
PCL
TTX
TEN
LLC
VSEL
EN
OTF
OLF
Function
These bits are read exactly the same as
they were left after last write operation
0
1
T
J
<140°C, normal operation
T
J
>150°C, power block disabled
I
OUT
<I
OMAX
, normal operation
I
OUT
>I
OMAX
, overload protection triggered
0
1
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