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參數(shù)資料
| 型號： | LMX2542 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLLatinum蜂窩頻率合成器和GPS系統(tǒng)的集成VCO |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 253K |
| 代理商： | LMX2542 |
Connection Diagram
Leadless Leadframe Package (LQ)
(Top View)
20082402
Note:
Analog GND connected through exposed die attached pad.
Pin Description
Pin No.
1
2
Pin Name
Fin
V
CC
I/O
I
—
Description
IF PLL buffer/prescaler input. Small signal input from the VCO.
Power supply bias for the IF PLL analog circuits. V
CC
may range from 2.7V to 3.3V.
Bypass capacitors should be placed as close as possible to this pin and be connected
directly to the ground plane on the printed circuit board.
IF PLL charge pump output. The output is connected to the external loop filter, which
drives the input of the IF VCO.
No Connect. Do not connect to any node on the printed circuit board.
MICROWIRE Latch Enable Input. High impedance CMOS input. When LE transitions
from LOW to HIGH, DATA stored in the shift register is loaded into one of 6 internal
control registers.
MICROWIRE Clock Input. High impedance CMOS input. DATA is clocked into the 24-bit
shift register on the rising edge of CLK.
MICROWIRE Data Input. High impedance CMOS input. Binary serial data. The MSB of
DATA is shifted in first.
Power supply bias for the RF VCO. V
DD
may range from 2.7V to 3.3V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
No Connect. Do not connect to any node on the printed circuit board.
Power supply bias for the RF VCO. V
DD
may range from 2.7V to 3.3V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane on the printed circuit board.
Power supply bias for the RF VCO output buffer. V
DD
may range from 2.7V to 3.3V.
Bypass capacitors should be placed as close as possible to this pin and be connected
directly to the ground plane on the printed circuit board.
Buffered RF VCO output.
Power supply bias for the RF PLL prescaler. V
CC
may range from 2.7V to 3.3V. Bypass
capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane on the printed circuit board.
3
CPout
O
4
5
NC
LE
—
I
6
CLK
I
7
DATA
I
8
V
DD
—
9
10
11
12
13
NC
NC
NC
NC
V
DD
—
—
—
—
—
14
V
DD
—
15
16
RFout
V
CC
O
—
L
www.national.com
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| LMX2542LQ2121 | 制造商:Texas Instruments 功能描述:IC PLL + VCO SMD 2542 LLP-28 |
| LMX2542LQ2121/NOPB | 功能描述:IC FREQ SYNTH CELL/GPS 28-LLP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2542LQX2121 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| LMX2571EVM | 功能描述:LMX2571 PLLatinum? Series Timing, Frequency Synthesizer Evaluation Board 制造商:texas instruments 系列:PLLatinum?? 零件狀態(tài):有效 主要用途:計時，頻率合成器 嵌入式:- 使用的 IC/零件:LMX2571 主要屬性:帶 VCO 的單路分?jǐn)?shù)-N PLL 輔助屬性:SMA 連接器 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| LMX2571NJKT | 功能描述:IC FREQ SYNTHESIZER VCO 制造商:texas instruments 系列:PLLatinum?? 包裝:剪切帶（CT） 零件狀態(tài):有效 類型:頻率合成器（RF） PLL:帶旁路 輸入:時鐘，晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:2:2 差分 - 輸入:輸出:是/無 頻率 - 最大值:1.4GHz 分頻器/倍頻器:是/是 電壓 - 電源:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-WFQFN 裸露焊盤 供應(yīng)商器件封裝:36-WQFN（6x6） 標(biāo)準(zhǔn)包裝:1 |
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