參數(shù)資料
型號: LMX2531LQ2265E
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: OPTOCOUPLER, TRANSISTOR O/P; Channels, No. of:1; Voltage, isolation:5300V; Output type:Transistor; Current, input:60mA; Voltage, output max:55V; Case style:DIL; Temperature, operating range:-55(degree C) to ?(degree C); Approval RoHS Compliant: Yes
中文描述: PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36
封裝: 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36
文件頁數(shù): 12/25頁
文件大?。?/td> 589K
代理商: LMX2531LQ2265E
2.0 General Programming Information
The LMX2531 is programmed using 14 24-bit registers used to control the LMX2531 operation. A 24-bit shift register is used as
a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The
last 4 register bits, CTRL[3:0] form the address field, which is used to decode the internal register address. The remaining 20 bits
form the data field DATA[19:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is
programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank.
Although there are actually 14 registers in this part, only a portion of them should be programmed, since the state of the other
hidden registers (R13, R11, and R10) are set during the initialization sequence. Although it is possible to program these hidden
registers, as well as a lot of bits that are defined to either ’1’ or ’0’, the user should not experiment with these bits, since doing so
may easily lead to degraded performance. The optimal settings for these bits have already been found, and not programming
them would not be consistent with how the part is tested.
DATA[19:0]
CONTROL[3:0]
MSB
D19
LSB
C0
D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 C3 C2 C1
2.01 Register Location Truth Table
C3
1
1
1
0
0
0
0
0
0
0
0
C2
1
0
0
1
1
1
1
0
0
0
0
C1
0
0
0
1
1
0
0
1
1
0
0
C0
0
1
0
1
0
1
0
1
0
1
0
Data Address
R12
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
2.02 Initialization Sequence
The initial loading sequence from a cold start is described below. The registers must be program in order shown.
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
C3 C2 C1 C0
R5
INIT1
R5
INIT2
R5
R12
R9
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
1
1
1
0
1
0
1
0
0
1
1
1
1
0
0
0
0
1
0
1
See individual section for R9 programming information.
See individual section for Register R8 programming information.
Register R8 only needs to be programmed for a few options of the LMX2531 and
and only in the case that the OSCin frequency is greater than 40 MHz.
See individual section for Register R7 programming information.
See individual section for Register R6 programming information.
See individual section for Register R4 programming information.
Register R4 only needs to be program if FastLock is used.
See individual section for Register R3 programming information.
See individual section for Register R2 programming information.
See individual section for Register R1 programming information.
See individual section for Register R0 programming information.
R8
1
0
0
0
R7
R6
0
0
1
1
1
1
1
0
R4
0
1
0
0
R3
R2
R1
R0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
Note: There must be a minimum of 10 mS between the time when R5 is last loaded and when R1 is loaded to ensure time for
the LDOs to power up properly.
2.03 Complete Register Content Map
L
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