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參數(shù)資料
| 型號： | LMX2531LQ2265E |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | OPTOCOUPLER, TRANSISTOR O/P; Channels, No. of:1; Voltage, isolation:5300V; Output type:Transistor; Current, input:60mA; Voltage, output max:55V; Case style:DIL; Temperature, operating range:-55(degree C) to ?(degree C); Approval RoHS Compliant: Yes |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 589K |
| 代理商： | LMX2531LQ2265E |
1.0 Functional Description
The LMX2531 is a low power, high performance frequency
synthesizer system which includes the PLL, VCO, and par-
tially integrated loop filter. Section 2.0 on programming de-
scribes the bits mentioned in this section in more detail.
1.1 Reference Oscillator Input
Because the VCO frequency calibration algorithm is based
on clocks from the OSCin pin, there are certain bits that need
to
be
set
depending
on
XTLSEL ( R6[22:20] ) and XTLDIV ( R7[9:8] ) are both need
to be set based on the OSCin frequency. For the
LMX2531LQ2080E
and
the
XTLMAN[11:0] and XTLMAN2.
the
OSCin
frequency.
LMX2531LQ2570E,
the
1.2 R Divider
The R divider divides the OSCin frequency down to the
phase detector frequency. The only valid R counter values
are 2, 4, 8, 16, and 32. The R divider also has an impact on
the fractional modulus that can be used, if it is greater than 8.
1.3 N Divider
The N divider on the LMX2531 is fractional and can achieve
any fractional denominator between 1 and 4,194,303 using a
delta-sigma modulator of selectable order of 2, 3, or 4.
Depending on the prescaler used, there are restrictions on
how small the N counter can be.
1.4 Phase Detector
The phase detector compares the outputs of the R and N
counters and puts out a correction current corresponding to
the phase error. The choice of the phase detector freqeuncy
does have an impact on performance.
1.5 Partially Integrated Loop Filter
The LMX2531 integrates the third pole (formed by R3 and
C3) and fourth pole (formed by R4 and C4) of the loop filter.
This loop filter can be enabled or bypassed using the
EN_LPFLTR ( R6[15] ). The values for C3, C4, R3, and R4
can also be programmed independently through the MI-
CROWIRE interface . Also, the values for R3 and R4 can be
changed during FastLock, for minimum lock time. It is rec-
ommended that the integrated loop filter be set to the maxi-
mum possible attenuation (R3=R4=40k
, C3=C4=100pF),
the internal loop filter is more effective at reducing certain
spurs than the external loop filter. However, the attenuation
of the internal loop filter is too high, it limits the maximum
attainable loop bandwidth that can be achieved, which cor-
responds to the case where the shunt loop filter capacitor,
C1, is zero. Increasing the charge pump current and/or the
comparison frequency increases the maximum attainable
loop bandwidth when desigining with the integrated filter.
Furthermore, this often allows the loop filter to be better
optimized and have stronger attenuation. If the charge pump
current and comparison frequency are already as high as
they go, and the maximum attainable loop bandwidth is still
too low, the resistor and capacitor values can be decreased
or the internal loop filter can even be bypassed. For design
tools and more information on partially integrated loop filters,
go to wireless.national.com.
1.6 Low Noise, Fully Integrated VCO
The LMX2531 includes a fully integrated VCO, including the
inductors. In order for optimum phase noise performance,
this VCO has frequency and phase noise calibration algo-
rithms. The VCO internally divides up the frequency range
into several bands, in order to achieve a lower tuning gain,
and therefore better phase noise performance. The fre-
quency calibration routine is activated any time that the R0
register is programmed. If the temperature shifts consider-
ably and the R0 register is not programmed, then it can not
drift more than continuous lock temperature range,
T
CL
, or
else the VCO is not guaranteed to stay in lock. There is also
a routine for optimum phase noise performance as well, for
each
version
of
VCO_ACI_SEL bit ( R6[19:16] ) needs to be set to the
correct value to ensure the best possible phase noise.
The gain of the VCO can change considerably over fre-
quency. It is lowest at the minimum frequency and highest at
the maximum frequency. This range is specified in the
datasheet. When designing the loop filter, the following
method is recommended. First, take the gemetric mean of
the minimum and maximum frequencies that are to be used.
Then use a linear approximation to extrapolate the VCO
gain. An example is in order. Suppose the application re-
quires the LMX2531LQ2080E PLL to tune from 2100 to 2150
MHz. The geometric mean of these freqeuncies is sqrt(2100
x 2150) MHz = 2125 MHz. The VCO gain is specified as 9
MHz/V at 1904 MHz and 20 MHz/V at 2274 MHz. Over this
range of 370 MHz, the VCO gain changes 11 MHz/volt. So at
2125 MHz, the VCO gain would be approximately 9 + (2125-
1904)* 11/370 = 15.6 MHz/V. Although the VCO gain can
change from part to part, this variation is small to how much
the VCO gain can change over frequency.
the
LMX2531,
the
1.7 Programmable Divide by 2
All options of the LMX2531 offer a divide by 2 option. This
allows the user to get exactly half of the VCO frequency. In
order to use this feature, the VCO is programmed to it’s
non-divided frequency. Note that R0 register should be re-
programmed the first time after the DIV2 bit is enabled or
disabled for optimal phase noise performance.
1.8 Choosing the Charge Pump Current and
Comparison Frequency
The LMX2531 has 16 levels of charge pump currents and a
highly flexible fractional modulus. This gives the user many
degrees of freedom. This section discusses some of the
design considerations. From the perspective of the PLL
noise, choosing the charge pump current and comparison
frequency as high as possible are best for optimal phase
noise performance. The far out PLL noise improves 3 dB for
every doubling of the comparison frequency, but at lower
offsets, this effect is much less due to the PLL 1/f noise.
Increasing the charge pump current inproves the phase
noise about 3 dB per doubling of the charge pump current,
although there are small diminishing returns as the charge
pump current goes higher.
So, from a loop filter design perspective and from a PLL
phase noise perspective, one might think to always design
with the highest possible comparison frequency and charge
pump current. However, if one considers the worst case
fractional spurs that occur at an output frequency equal to 1
channel spacing away from a multiple of the OSCin fre-
quency, then this gives reason to reconsider. If the compari-
son frequency or charge pump currents are too high, then
these spurs could be degraded, and the loop filter may not
be able to filter these spurs as well as theoretically predicted.
For optimal spur performance, a comparison frequency in
the ballpark of 2.5 MHz and a charge pump current of 1X are
recommended.
L
www.national.com
11
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