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參數(shù)資料
| 型號： | LMX2531LQ1910E |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum High Performance Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 80 MHz, QCC36 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, LEAD FREE, LLP-36 |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 589K |
| 代理商： | LMX2531LQ1910E |
2.0 General Programming Information
(Continued)
2.1 REGISTER R0
Note that the action of programming the R0 register activates a calibration routine for the VCO. This calibration is necessary to
get the VCO to center the tuning voltage for optimal performance. If the temperature drifts considerably, then the PLL should stay
in lock, provided that the temperature drift specification is not violated.
2.1.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator
The NUM word is split between the R0 register and R1 register. The Numerator bits determine the fractional numerator for the
delta sigma PLL. This value can go from 0 to 4095 when the FDM bit ( R3[22] ) is 0 (the other bits in this register are ignored),
or 0 to 4194303 when the FDM bit is 1.
NUM[21:12]
NUM[11:0]
Fractional
Numerator
0
...
409503
4096
...
4194303
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note that there are restrictions on the fractional numerator value depending on the R counter value. These restrictions are related
to the coarse tuning algorithm of the VCO. A numerator value of zero is the exception and is always allowed. If the R counter is
≤
8, then there is no restriction on the fractional numerator. If R
>
8, the LSB of the fractional numerator must be 0. If R
>
16, the
two LSB bits of the fractional numerator must be 0. If R
>
32, the three LSB bits of the fractional numerator must be 0. If this
becomes an issue, recall that smaller fractions can be expressed as larger ones. For instance, 1/65 can be expressed as 8/520.
2.1.2 N[7:0] and N[10:8]
The N counter is 11 bits. 8 of these bits are located in the R0 register, and the remaining 3 (MSB bits) are located in the R1
register. The LMX2531 consists of an A, B, and C counter, which work in conjunction with the prescaler in order to form the final
N counter value.
Operation with the 8/9/12/13 Prescaler
N[10:8]
N[7:0]
N Value
<
31
31
...
1023
C
B
A
Values less than 31 are prohibited.
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
Operation with the 16/17/20/21 Prescaler
N[10:8]
N[7:0]
N Value
<
55
55
...
2039
C
B
A
Values less than 55 are prohibited.
0
0
0
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
L
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| LMX2531LQ2010E/NOPB | 功能描述:IC PLL FREQ SYNTH W/VCO 36-LLP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PowerWise® 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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