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參數(shù)資料
| 型號： | LMX2525LQ1321 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Dual Frequency Synthesizer System with Integrated VCOs |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC24 |
| 封裝： | 5 X 4 MM, 0.75 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 237K |
| 代理商： | LMX2525LQ1321 |
Electrical Characteristics
(V
IN
= 2.8 V, refer to Typical Application Circuit; Limits in standard typeface are for
T
A
= 25 C; Limits in
boldface
type apply over the operating temperature range from -20 C
≤
T
A
≤
75 C unless otherwise
noted.) (Continued)
Symbol
RF2 VCO FOR PDC800
Spurious Tones
Parameter
Condition
Min
Typ
Max
Units
@
≤
25 kHz offset
@
25 kHz
<
offset
≤
50 kHz
@
50 kHz
<
offset
≤
100 kHz
@
offset
>
100 kHz
-45
-60
-69
-75
dBc
dBc
dBc
dBc
DIGITAL INTERFACE (DATA, CLK, LE, LD, CE, BS)
V
IH
High-Level Input Voltage
0.8 V
CC
0.8 V
DD
-0.3
-0.3
-10
-10
V
CC
V
DD
0.2 V
CC
0.2 V
DD
10
10
V
V
V
V
μA
μA
pF
ns
V
V
V
pF
V
IL
Low-Level Input Voltage
I
IH
I
IL
High-Level Input Current
Low-Level Input Current
Input Capacitance
Rise/Fall Time
High-Level Output Voltage
3
30
V
OH
V
CC
- 0.4
V
DD
- 0.4
V
OL
Low-Level Output Voltage
Output Capacitance
MICROWIRE INTERFACE TIMING
t
CS
Data to Clock Set Up Time
t
CH
Data to Clock Hold Time
t
CWH
Clock Pulse Width HIGH
t
CWL
Clock Pulse Width LOW
t
DS
Latch Enable LOW to Data Set Up
Time
t
ES
Clock to Latch Enable Set Up Time
t
EW
Latch Enable Pulse Width
0.4
5
50
10
50
50
50
ns
ns
ns
ns
ns
50
50
ns
ns
Note 5:
RF PLL and VCO in PDC800 mode.
Note 6:
RF PLL and VCO in PDC1500 mode.
Note 7:
The reference frequency must be programmed using the OSC_FREQ control bit. For other reference frequencies, please contact National Semiconductor.
Note 8:
For other frequency ranges, please contact National Semiconductor.
Note 9:
Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/-1 kHz
of the final frequency.
Note 10:
Lock time is defined as the time difference between the beginning of the frequency transition and the point at which the frequency remains within +/-3 kHz
of the final frequency.
Note 11:
Lock time specification also applies to power up with MICROWIRE serial interface.
Note 12:
All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with T
A
= 25 C or correlated using
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
L
www.national.com
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2525LQ1321/NOPB | 功能描述:IC FREQ SYNTH DUAL W/VC0 24-LLP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:100 系列:* |
| LMX2525LQX1321 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Dual Frequency Synthesizer System with Integrated VCOs |
| LMX2525LQX1321/NOPB | 功能描述:IC FREQ SYNTH DUAL VCO 24-LLP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:100 系列:* |
| LMX2531 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Frequency Synthesizer System with Integrated VCO |
| LMX2531_07 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Frequency Synthesizer System with Integrated VCO |
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