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參數(shù)資料
| 型號： | LMX2515LQ1321/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁數(shù)： | 3/17頁 |
| 文件大?。?/td> | 254K |
| 代理商： | LMX2515LQ1321/NOPB |
Functional Description (Continued)
HIGH SPEED LOCK-UP MODE
Two frequency-locking modes are provided: a Normal mode
and a High Speed mode for faster lock times. The HS bit in
register R0 controls the locking mode.
TABLE 5. Lock-up Modes
HS Bit
Mode
0
Normal mode
1
High Speed mode
MICROWIRE INTERFACE
The programmable register set is accessed via the
MICROWIRE serial interface. The interface is comprised of
three signal pins: CLK, DATA, and LE (Latch Enable). Serial
data is clocked into the 24-bit shift register on the rising edge
of the clock. The last bits decode the internal control register
address. When the latch enable (LE) transitions from LOW
to HIGH, data stored in the shift registers is loaded into the
corresponding control register. The data is loaded MSB first.
20068809
FIGURE 3. Lock Detect Flow Diagram
LMX2515
www.national.com
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