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參數(shù)資料
| 型號： | LMX2515LQ1321/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC28 |
| 封裝： | 5 X 5 MM, 0.75 MM HEIGHT, LLP-28 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大小： | 254K |
| 代理商： | LMX2515LQ1321/NOPB |
Functional Description (Continued)
TABLE 1. Power Down Modes
CE pin
RF_PD Bit
Mode
HIGH
0
Active
HIGH
1
Not Active
LOW
0
Not Active
LOW
1
Not Active
VCO SELECTION
The RF_SEL bit must be used to select the RF VCO output.
When using the LMX2515LQ0701 the RF_SEL bit must be
set to "0". When using the LMX2515LQ1321 the RF_SEL bit
must be set to "1".
TABLE 2. VCO Selection
RF_SEL Bit
Mode
0
LMX2515LQ0701
1
LMX2515LQ1321
LOCK DETECT MODE
The LD output can be used to indicate the lock status of the
PLL. Bit 6 in Register R1 determines the signal that appears
on the LD pin. When the PLL is not locked, the LD pin
remains LOW. After obtaining phase lock, the LD pin will
have a logical HIGH level. The LD output is always low when
the LD register bit is 0 and in power down mode.
TABLE 3. Lock Detect Modes
LD Bit
Mode
0
Disable (GND)
1
Enable
TABLE 4. Lock Detect Logic
RF-PLL Section
LD Output
Locked
HIGH
Not Locked
LOW
Note 13: LD output becomes low when the phase error is larger than tW2.
Note 14: LD output becomes high when the phase error is less than tW1 for
four or more consecutive cycles.
Note 15: Phase Error is measured on leading edge. Only errors greater than
tW1 and tW2 are labeled.
Note 16: tW1 is 5 ns for LMX2515LQ1321 and 10 ns for LMX2515LQ0701.
tW2 is 10 ns for both devices.
Note 17: The lock detect comparison occurs with every 64th cycle of fR and
fN
20068808
FIGURE 2. Lock Detect Timing Diagram Waveform (Notes 13, 14, 15, 16, 17)
LMX2515
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