參數(shù)資料
型號(hào)： LMX2502LQX1635
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： PLLatinum⑩ Frequency Synthesizer System with Integrated VCO
中文描述： PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28
封裝： 5 X 5 MM, 0.75 MM HEIGHT, LLP-28
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 184K
代理商： LMX2502LQX1635
Functional Description
(Continued)
TABLE 2. Power Down Configuration
CE Pin
0
1
1
1
1
RF_EN
X
0
0
1
1
IF_EN
X
0
1
0
1
RF Circuitry
OFF
OFF
OFF
ON
ON
IF Circuitry
OFF
OFF
ON
OFF
ON
X = Don’t care.
LOCK DETECT
The LD output can be used to indicate the lock status of the
RF PLL. Bit 21 in Register R0 determines the signal that
appears on the LD pin. When the RF PLL is not locked, the
LD pin remains LOW. After obtaining phase lock, the LD pin
will have a logical HIGH level. The output can also be
programmed to be ground at all times.
TABLE 3. Lock Detect Modes
LD Bit
0
1
Mode
Disable (GND)
Enable
TABLE 4. Lock Detect Logic
RF PLL Section
Locked
Not Locked
LD Output
HIGH
LOW
Note 9:
LD output becomes LOW when the phase error is larger than t
W2
.
Note 10:
LD output becomes HIGH when the phase error is less than t
W1
for
four or more consecutive cycles.
Note 11:
Phase Error is measured on leading edge. Only errors greater than
t
W1
and t
W2
are labeled.
Note 12:
t
W1
and t
W2
are equal to 10 ns.
Note 13:
The lock detect comparison occurs with every 64
th
cycle of f
R
and
f
N
.
20068005
FIGURE 1. Lock Detect Timing Diagram Waveform
(Notes 9, 10, 11, 12, 13)
L
www.national.com
8
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2505 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinu Dual Frequency Synthesizer System with Integrated VCOs
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LMX2505LQ1321 制造商:Texas Instruments 功能描述:PLL VCO CDMA SMD 2505 LLP-28
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