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參數(shù)資料
| 型號： | LMX2353SLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| 中文描述： | PHASE LOCKED LOOP, 2500 MHz, CQCC16 |
| 封裝： | PLASTIC, CSP-16 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 210K |
| 代理商： | LMX2353SLBX |
1.0 Functional Description
(Continued)
1.3.2 Fractional Compensation
The fractional compensation circuitry in the N divider allows the user to adjust the VCO’s tuning resolution in 1/16 or 1/15 incre-
ments of the phase detector comparison frequency. A 4-bit register is programmed with the fractions desired numerator, while an-
other bit selects between fractional 15 and 16 modulo base denominator. An integer average is accomplished by using a 4-bit ac-
cumulator. A variable phase delay stage compensates for the accumulated integer phase error, minimizing the charge pump duty
cycle, and reducing spurious levels. This technique eliminates the need for compensation current injection in to the loop filter.
Overflow signals generated by the accumulator are equivalent to 1 full VCO cycle, and result in a pulse swallow.
1.4 PHASE/FREQUENCY DETECTOR
The phase/frequency detector is driven from the N and R counter outputs. The maximum frequency at the phase detector input
is about 2 MHz for some high frequency VCO due to the minimum continuous divide ratio of the dual modulus prescaler. For ex-
ample, if the VCO output frequency is 1.984 GHz, the maximum phase detector input frequency is 2 MHz because the minimum
continuous divide ratio with 32/33 prescaler is 1056. The phase detector outputs control the charge pumps. The polarity of the
pump-up or pump-down control is programmed using PD_POL depending on whether the VCO characteristics are positive or
negative. The phase detector also receives a feedback signal from the charge pump, in order to eliminate dead zone.
1.5 CHARGE PUMPS
The phase detector’s current source output pumps charge into an external loop filter, which then integrates into the VCO’s control
voltage. The charge pump steers the charge pump output CP
to V
(pump-up) or Ground (pump-down). When locked, CP
is
primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected from 100 μA
to 1.6 mA by programming the
CP_WORD
bits.
1.6 VOLTAGE DOUBLER
The V
pin is normally driven from an external power supply over a range of V
to 5.5V to provide current for the RF charge
pump circuit. An internal voltage doubler circuit connected between the V
and V
supply pins alternately allows V
= 3V
(
±
10%) users to run the RF charge pump circuit at close to twice the V
power supply voltage. The Voltage doubler mode is en-
abled by setting the V2_EN bit (R[20]) to a HIGH level. The average delivery current of the doubler is less than the instantaneous
current demand of the RF charge pump when active and is thus not capable of sustaining a continuous out of lock condition. A
large external capacitor connected to V
p
(
≈
0.1 μF) is therefore needed to control power supply droop when changing frequencies.
1.7 MICROWIRE
SERIAL INTERFACE
The programmable functions are accessed through the MICROWIRE serial interface. The interface is made of three functions:
clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the rising edge of clock, into the
24-bit shift register. Data is entered MSB first. The last two bits decode the internal register address. On the rising edge of LE,
data stored in the shift register is loaded into one of the 4 appropriate latches (selected by address bits).Acomplete programming
description is included in the following sections.
1.8 Lock Detect Output
A digital filtered lock detect function is included with each phase detector through an internal digital filter to produce a logic level
output available on the FoLD output pin if selected. The lock detect output is high when the error between the phase detector in-
puts is less than 15 ns for 5 consecutive comparison cycles. The lock detect output is low when the error between the phase de-
tector inputs is more than 30 ns for one comparison cycle. An analog lock detect status generated from the phase detector is also
available on the FoLD output pin, if selected. The lock detect output goes high when the charge pump is inactive. It goes low when
the charge pump is active during a comparison cycle. When a PLL is in power down mode, the respective lock detect output is
always low.
1.9 OUT0/OUT1 Output Modes (Fastlock & CMOS Output Modes)
The OUT_0 and OUT_1 pins are normally used as general purpose CMOS outputs or as part of a fastlock scheme. There is also
a production test mode that overrides the other two normal modes when activated. The selection of these modes is determined
by the 4 bit CMOS register (F2_15–18) described in Table 2.5.3.
The fastlock mode allows the user to open up the loop bandwidth momentarily while acquiring lock by increasing the charge pump
output current magnitude while simultaneously switching in a second resistor element to ground via the OUT0 output pin. The
loop will lock faster without any additional stability considerations as the phase margin remains constant.
The loop bandwidth during fastlock can be opened up by as much as a factor of 4. The amount of bandwidth increase is a function
of the square root of the charge pump current increase. The maximum charge pump current ratio results from switching the
charge pump current between 100 μA and 1.6 mA. The damping resistor ratio for these two charge pump current setting changes
by the reciprocal of the bandwidth change. In the 4 to 1 bandwidth scenerio, the resulting damping resistor value would be 1/4th
of the steady state value. This would be achieved by switching 3 more identical resistors in parallel with the first to ground through
the OUT_0 pin.
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| LMX2353TMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| LMX2353TMX/NOPB | 功能描述:IC FREQ SYNTH 2.5GHZ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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