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參數(shù)資料
| 型號： | LMX2336LSLB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC24 |
| 封裝： | PLASTIC, CSP-24 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 542K |
| 代理商： | LMX2336LSLB |
Functional Description
(Continued)
TABLE 3. The F
o
LD Output Truth Table
RF1 R[19]
(RF1 LD)
0
0
1
1
X
X
X
X
0
0
1
1
RF2 R[19]
(RF2 LD)
0
1
0
1
0
0
1
1
0
1
0
1
RF1 R[20]
(RF1 F
O
)
0
0
0
0
0
1
0
1
1
1
1
1
RF2 R[20]
(RF2 F
O
)
0
0
0
0
1
0
1
0
1
1
1
1
F
o
LD
Output State
Disabled (Note 10)
RF2 Lock Detect (Note 11)
RF1 Lock Detect (Note 11)
RF1/RF2 Lock Detect (Note 11)
RF2 Reference Divider Output
RF1 Reference Divider Output
RF2 Programmable Divider Output
RF1 Programmable Divider Output
Fastlock (Note 12)
RF2 Counter Reset (Note 13)
RF1 Counter Reset (Note 13)
RF1 and RF2 Counter Reset (Note 13)
X — don’t care condition
Note 10:
When the F
o
LD output is disabled it is actively pulled to a low logic state.
Note 11:
Lock detect output provided to indicate when the VCO frequency is in “l(fā)ock”. When the loop is locked and a lock detect mode is selected, the pins output
is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked.
Note 12:
The Fastlock mode utilized the F
LD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock
occurs whenever the RF loop’s Icpo magnitude bit
#
17 is selected HIGH (while the
#
19 and
#
20 mode bits are set for Fastlock).
Note 13:
The RF2 counter reset mode resets RF2 PLL’s R and N counters and brings RF2 charge pump output to a TRI-STATE condition. The RF1 counter reset
mode resets RF1 PLL’s R and N counters and brings RF1 charge pump output to a TRI-STATE condition. The RF1 and RF2 counter reset mode resets all counters
and brings both charge pump output to a TRI-STATE condition. Upon removal of the Reset bits the N counter resumes counting in “close” alignment with the R
counter. (The maximum error is one prescaler cycle).
POWERDOWN OPERATION
Synchronous and asynchronous powerdown modes are
both available by microwire selection. Synchronously power-
down occurs if the respective loop’s R18 bit (Do TRI-STATE)
is LOW when its N20 bit (Pwdn) becomes HI. Asynchronous
powerdown occurs if the loop’s R18 bit is HI when its N20 bit
becomes HI.
In the synchronous powerdown mode, the powerdown func-
tion is gated by the charge pump to prevent unwanted fre-
quency jumps. Once the powerdown program bit N20 is
loaded, the part will go into powerdown mode when the
charge pump reaches a TRI-STATE condition.
In the asynchronous powerdown mode, the device powers
down immediately after the LE pin latches in a HI condition
on the powerdown bit N20.
Activation of either the IF or RF PLL powerdown conditions
in either synchronous or asynchronous modes forces the re-
spective loop’s R & N dividers to their load state condition
and debiasing of it’s respective Fin input to a high imped-
ance state. The oscillator circuitry function does not become
disabled until both IF and RF powerdown bits are activated.
The MICROWIRE control register remains active and ca-
pable of loading and latching data during all of the power-
down modes.
The device returns to an actively powered up condition in ei-
ther synchronous ar asynchronous modes immediately upon
LE latching LOW data into bit N20.
Powerdown Mode Select Table
R18
0
1
N20
0
0
Powerdown Status
PLL Active
PLL Active (Charge Pump Output
TRI-STATE)
Synchronous Powerdown Initiated
Asynchronous Powerdown Initiated
0
1
1
1
www.national.com
13
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