參數(shù)資料
型號: LMX2305TMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: PLLatinumTM 550 MHz Frequency Synthesizer for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 550 MHz, PDSO20
封裝: 0.173 INCH, PLASTIC, TSSOP-20
文件頁數(shù): 8/14頁
文件大?。?/td> 228K
代理商: LMX2305TMX
Functional Description
(Continued)
SERIAL DATA INPUT TIMING
TL/W/12459–16
Notes:
Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions:
The Serial Data Input Timing is tested using a symmetrical waveform around V
CC
/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V
@
V
CC
e
2.7V and 2.6V
@
V
CC
e
5.5V.
Phase Characteristics
In normal operation, the FC pin is used to reverse the polari-
ty of the phase detector. Both the internal and any external
charge pump are affected.
Depending upon VCO characteristics, FC pin should be set
accordingly:
When VCO characteristics are like (1), FC should be set
HIGH or OPEN CIRCUIT;
When VCO characteristics are like (2), FC should be set
LOW.
When FC is set HIGH or OPEN CIRCUIT, the monitor pin of
the phase comparator input, f
out
, is set to the reference
divider output, f
r
. When FC is set LOW, f
out
is set to the
programmable divider output, f
p
.
VCO Characteristics
TL/W/12459–17
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
TL/W/12459–18
Notes:
Phase difference detection range:
b
2
q
to
a
2
q
The minimum width pump up and pump down current pulses occur at the D
o
pin when the loop is locked.
FC
e
HIGH
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