參數(shù)資料
型號(hào): LMX2305TMX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): XO, clock
英文描述: PLLatinumTM 550 MHz Frequency Synthesizer for RF Personal Communications
中文描述: PLL FREQUENCY SYNTHESIZER, 550 MHz, PDSO20
封裝: 0.173 INCH, PLASTIC, TSSOP-20
文件頁(yè)數(shù): 6/14頁(yè)
文件大?。?/td> 228K
代理商: LMX2305TMX
Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the R15 Latch, and the 18-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter
(programmable divider).
TL/W/12459–1
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND PRESCALER SELECT (R15 LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch, which sets the prescaler: 64/65 or 128/129. Serial data format
is shown below.
TL/W/12459–14
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
Divide
Ratio
R
14
R
13
R
12
R
11
R
10
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
1
#
0
#
0
#
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
R1 to R14: These bits select the divide ratio of the programmable
reference divider.
C: Control bit (set to HIGH level to load R counter and R15 Latch)
Data is shifted in MSB first.
1-BIT PRESCALER SELECT
(R15 LATCH)
Prescaler
Select
P
15
R
128/129
0
64/65
1
http://www.national.com
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相關(guān)PDF資料
PDF描述
LMX2305 PLLatinum 550 MHz Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的550MHZ頻率合成器)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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