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參數(shù)資料
| 型號(hào)： | LMS1145M |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO24 |
| 封裝： | SOIC-24 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 151K |
| 代理商： | LMS1145M |
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC5V
7V
PWRGD
(V
CC 5V + 0.2V)
V
CC12V
20V
Junction Temperature
125C
Power Dissipation (Note 2)
1.6W
Storage Temperature
65C to +150C
ESD Susceptibility (Note 8)
2 kV
Soldering Time, Temperature
10 sec., 300C
Operating Ratings (Note 1)
V
CC 5V
4.5V to 5.5V
V
CC 12V
10V to 18V
Junction Temperature Range
0C to 70C
Electrical Characteristics
V
CC5V = 5V, VCC12V = 12V unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ = +25C.
Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
V
DACOUT
5-bit DAC Output Voltage
(Note 3)
N1.5%
NN+1.5%
V
I
CC12V
Quiescent V
CC12V Current
Enable = 5V, VID = 00001,
DRV Outputs Floating
1
2
mA
I
CC5V
Operating V
CC5V Current
V
OUT = 2.00V
4.3
8
mA
V
REF
Rref Pin Voltage
1.225
V
INL
Vid0:4, Clksel, Divsel, and
Enable Pins Logic Threshold
Logic Low (Note 4)
1.8
1.5
V
INH
Logic High (Note 5)
3.5
2.8
V
I
INL
Vid0:4 and Enable Pins Internal
Pullup Current
The Corresponding Pin = 0V
60
100
140
A
Clksel, Divsel Pins Internal
Pullup Current
10
0
10
Gate Driver Resistance When
Sinking Current
I
SINK = 50 A, VCC12V = 14V
12
V
DRV
DRV0:3 Output Voltage
I
DRV = 10 mA, VCC12V = 14V
V
CC12V
1.5V
V
CC12V
1.0V
V
t
fall
DRV0:3 Fall Time
(Note 6)
7
ns
I
SRC
DRV0:3 Source Current
DRV0:3 = 0V, V
CC12V = 14V
40
60
mA
I
SINK
DRV0:3 Sink Current
DRV0:3 = 5V, V
CC12V = 14V
90
160
250
mA
VB
gOUT
B
gOUT Voltage
Current Limit Not Activated
4
V
Current Limit Activated
0
IB
gOUT
B
gOUT Sink Current
B
gOUT = 1V
1.0
2.4
5
mA
I
FB
FB Pin Bias Current
FB = 2V
30
nA
F
OSC
Oscillator Frequency
8.02k
from Rref Pin to
Ground
7.0
8.0
8.7
MHz
D
DRV0:3 Duty Cycle Match
Duty Cycle = 50%
1
+1
%
ph
DRV0:3 Phase Accuracy
Duty Cycle = 50%,F
clock = 8
MHz
1
+1
Deg
T
off
PWM Off time
Divide by 4
22
%
Divide by 3
22
V
PWRGD
Power Good Detection
Window,
V
OUT
1.3V
≤ V
OUT ≤ 1.9V
±100
mV
Hysteresis
50
Power Good Detection
Window,
V
OUT
2V
≤ V
OUT ≤ 3.5V
±150
Hysteresis
50
LMS1
145
www.national.com
2
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