參數(shù)資料
型號： LMK04000BEVAL/NOPB
廠商： National Semiconductor
文件頁數(shù)： 49/65頁
文件大?。?/td> 0K
描述： BOARD EVAL PRECISION CLOCK PLL
標準包裝： 1
系列： PowerWise®
主要目的： 計時，時鐘調節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04000
主要屬性： 122.88 MHz VCXO
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
其它名稱： LMK04000BEVAL
LMK04000BEVAL-ND
CLKoutX
CLKoutX*
1
2
0
:
1
2
0
:
0.1 PF
LVPECL
Receiver
100: Trace
(Differential)
LVPECL
Driver
8
2
:
1
2
0
:
Vcc
8
2
:
1
2
0
:
Vcc
0.1 PF
LVDS
Receiver
100: Trace
(Differential)
LVDS
Driver
1
0
:
CLKoutX
CLKoutX*
0.1 PF
LVDS
Receiver
5
0
:
100: Trace
(Differential)
LVDS
Driver
5
0
:
Vbias
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Termination for AC Coupled Differential Operation
AC coupling allows for shifting the DC bias level (common mode voltage) when driving different receiver
standards. Since AC coupling prevents the driver from providing a DC bias voltage at the receiver it is important
to ensure the receiver is biased to its ideal DC level.
When driving non-biased LVDS receivers with an LVDS driver, the signal may be AC coupled by adding DC
blocking capacitors, however the proper DC bias point needs to be established at the receiver. One way to do
this is with the termination circuitry in Figure 21.
Figure 21. Differential LVDS Operation, AC Coupling, External Biasing at the Receiver
Some LVDS receivers may have internal biasing on the inputs. In this case, the circuit shown in Figure 21 is
modified by replacing the 50
Ω terminations to Vbias with a single 100 Ω resistor across the input pins of the
receiver, as shown in Figure 22. When using AC coupling with LVDS outputs, there may be a startup delay
observed in the clock output due to capacitor charging. The previous figures employ a 0.1 F capacitor. This
value may need to be adjusted to meet the startup requirements for a particular application.
Figure 22. LVDS Termination for a Self-Biased Receiver
LVPECL drivers require a DC path to ground. When AC coupling an LVPECL signal use 120
Ω emitter resistors
close to the LVPECL driver to provide a DC path to ground as shown in Figure 23. For proper receiver operation,
the signal should be biased to the DC bias level (common mode voltage) specified by the receiver. The typical
DC bias voltage for LVPECL receivers is 2 V. A Thevenin equivalent circuit (82
Ω resistor connected to VCC and
a 120
Ω resistor connected to ground with the driver connected to the junction of the 82 Ω and 120 Ω resistors) is
a valid termination as shown in Figure 23 for VCC = 3.3 V. Note this Thevenin circuit is different from the DC
coupled example in Figure 20.
Figure 23. Differential LVPECL Operation, AC Coupling, Thevenin Equivalent, External Biasing at the
Receiver
Copyright 2008–2011, Texas Instruments Incorporated
53
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相關代理商/技術參數(shù)
參數(shù)描述
LMK04000BEVALXO 功能描述:時鐘和定時器開發(fā)工具 LMK04000 EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
LMK04000BISQ 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04000BISQ/NOPB 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
LMK04000BISQE 制造商:Texas Instruments 功能描述:Clock Conditioner 48-Pin LLP EP T/R
LMK04000BISQE/NOPB 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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