Application Notes
(Continued)
POWER CONSUMPTION
Power consumption is a function of line power and dynamic
bias current of the line driver.After the transformer turns ratio
has been selected as described above, power consumption
per channel for the typical R-C termination application can
be estimated as follows:
I
CC
= IdB + I
LOAD
IdB = 0.25 * Iq
This is because 25% of the total dc current flows in the
output transistors. This term effectively vanishes when the
class AB stage is drives a heavy load.
Where I
LOAD
= average load current driven by output
transistors
IdB = dynamic V
CC
bias current while driving full load
power
I
CC
= average V
CC
current
When losses included, 103.5 mW is delivered by the driver,
therefore
I
RMS
= TR*
√
(.1035/100) = 32.2 mA
Since the ADSL signal is DMT and is effectively guassian,
the average value of the supply current due to driving the
load is given by
I
LOAD
= average|I
RMS
| =
√
(2/
π
)*I
RMS
= 0.8 * I
RMS
= 44.6
mA for TR = 1.73
Assuming 2/3 power mode, Ifixed = 0.25 * 11 mA = 2.75 mA
I
CC
= 2.75 mA + 44.6 mA = 47.4 mA
P
CC
= I
CC
x V
CC
= 569 mW
To get the I
DD
full current, simply add 0.75 mA to the quies-
cent current per channel:
I
DD
= 0.75 + 5.5 + 0.6 = 6.8 mA
P
DD
= V
DD
* I
DD
= 23 mW
For the total power consumption per channel,
P
CON
= P
DD
+ P
CC
= 592 mW
For power dissipation of the LMH6678, subtract the power
into the load plus external losses:
P
DISS
= 592-103 = 489 mW per channel
P
DISS
total = 2 x 489 = 978 mW for both channels
Proper selection of the external resistor between theADJ pin
can optimize the trade-off between power consumption and
distortion. This external resistor will reduce the supply cur-
rent for the 1/3, 2/3 and full bias settings for both channels.
The approximately equation is
I
S
= I
S
* (1- (V
CC
-0.8)/(30μA*R
ADJ
))
Curves of V
and V
supply currents per channel vs. R
for the various power settings are shown in typical perfor-
mance characteristics section.
PACKAGE AND LAYOUT CONSIDERATION
The LMH6678 uses the 24-pin Leadless Leadframe Pack-
age, a thermally enhanced, standard size IC package de-
signed to eliminate the use of bulky heatsinks traditionally
used in thermal packages. This package can be easily
mounted using standard PCB surface mount assembly tech-
niques.
The LLP is designed so that the thermal pad is exposed on
the bottom of the IC, as shown in the package drawing. This
provides an extremely low thermal resistance (
θ
) path
between the die and the exterior of the package. The thermal
pad on the bottom of the IC can then be soldered directly to
the PCB, using the PCB as a heatsink. In addition, plated-
through holes (vias) on the PCB provide a low thermal
resistance heat flow path to the backside of the circuit board.
LAND PATTERN AND ASSEMBLY GUIDELINE FOR
LMH6678
1.
The thermal pad must be connected to analog ground
AGND in LMH6678.
2.
Prepare the PCB with a top-side land pattern, as shown
in figure 8.
3.
Place the recommended number of plated-through holes
in the area of the thermal pad. These holes should be 8
mils max. in diameter. They are kept small so that solder
wicking through the holes is not a problem during reflow.
The minimum recommended number of holes for the
24-pin LLP is six, as shown in
Figure 8
.
4.
Connect all holes to the internal and bottom analog
ground plane.
5.
When laying out these holes to the ground plane, do not
use the typical web or spoke via connection methodol-
ogy, as shown in
Figure 9
. Web connections have a high
thermal resistance connection that is useful for slowing
the heat transfer during soldering operations. This
makes soldering the vias that have ground plane con-
nections easier. However, in this application, low thermal
resistance is desired for the most efficient heat transfer.
Therefore, the holes under the thermal pad should make
their connection to the internal ground plane with a
complete connection around the entire circumference of
the plated-through hole. Use plated via with solid con-
nection to plane as shown in
Figure 10
.
6.
The top-side solder mask should leave the terminals of
the pad connections and the thermal pad area exposed.
The thermal pad area should leave the 8 mils holes
exposed.
7.
Apply solder paste to the exposed thermal pad area and
all of the package terminals.
8.
With these preparatory steps in place, the LLP is simply
placed in position and run through the solder reflow
operation as any standard surface-mount component.
This results in a part that is properly installed.
20084050
FIGURE 8. Recommended Land Pattern
L
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