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| 型號(hào)： | LMF40 |
| 文件頁(yè)數(shù)： | 8/16頁(yè) |
| 文件大小： | 321K |
| 代理商： | LMF40 |
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Pin Descriptions
(Numbers in ( ) are for 14-pin package).
Pin
Y
1
(1)
Pin
Name
CLK IN
Function
A CMOS Schmitt-trigger input
to be used with an external
CMOS logic level clock. Also
used for self clocking Schmitt-
trigger oscillator (see Section
1.1).
A TTL logic level clock input
when in split supply operation
(
g
2.0V to
g
7V) with L. Sh
tied to system ground. This pin
becomes a low impedance
output when L. Sh is tied to
V
b
. Also used in conjunction
with the CLK IN pin for a self
clocking Schmitt-trigger
oscillator (see Section 1.1).
The TTL input signal must not
exceed the supply voltages by
more than 0.2V.
Level shift pin; selects the
logic threshold levels for the
clock. When tied to V
b
it
enables an internal TRI-
STATE
é
buffer stage between
the Schmitt trigger and the
internal clock level shift stage
thus enabling the CLK IN
Schmitt-trigger input and
making the CLK R pin a low
impedance output. When the
voltage level at this input
exceeds 25% (V
a
b
V
b
)
a
V
b
the internal TRI-STATE
buffer is disabled allowing the
CLK R pin to become the
clock input for the internal
clock level-shift stage. The
CLK R threshold level is now
2V above the voltage on the L.
Sh pin. The CLK R pin will be
compatible with TTL logic
levels when the LMF40 is
operated on split supplies with
the L. Sh pin connected to
system ground.
The output of the low-pass
filter.
The analog ground pin. This
pin sets the DC bias level for
the filter section and must be
tied to the system ground for
split supply operation or to
mid-supply for single supply
operation (see Section 1.2).
When tied to mid-supply this
pin should be well bypassed.
2
CLK R
(3)
3
L. Sh
(5)
5
FILTER
OUT
AGND
(8)
6
(10)
Pin
Y
7, 4
(7, 12)
Pin
Name
V
a
, V
b
Function
The positive and negative
supply pins. The total power
supply range is 4V, to 14V.
Decoupling these pins with
0.1
m
F capacitors is highly
recommended.
The input to the low-pass filter.
To minimize gain errors the
source impedance that drives
this input should be less than
2k (see Section 3). For single
supply operation the input
signal must be biased to mid-
supply or AC coupled through
a capacitor.
8
FILTER
IN
(14)
1.0 LMF40 Application Information
The LMF40 is a non-inverting unity gain low-pass fourth-or-
der Butterworth switched-capacitor filter. The switched-ca-
pacitor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or
50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filter’s cutoff frequency.
The resistive element of these integrators is actually a ca-
pacitor which is ‘‘switched’’ at the clock frequency (for a
detailed discussion see Input Impedance section). Varying
the clock frequency changes the value of this resistive ele-
ment and thus the time constant of the integrators. The
clock-to-cutoff-frequency ratio (f
CLK
/f
c
) is set by the ratio of
the input and feedback capacitors in the integrators. The
higher the clock-to-cutoff-frequency ratio the closer this ap-
proximation is to the theoretical Butterworth response.
1.1 CLOCK INPUTS
The LMF40 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R/C oscillator. Pin 3 is con-
nected to V
b
, making Pin 2 a low impedance output. The
oscillator’s frequency is nominally
f
CLK
e
1
RC In
V
CC
b
V
t
b
V
CC
b
V
t
a
V
t
a
V
t
b
(1)
which is typically
f
CLK
j
1
1.37 RC
(1a)
for V
CC
e
10V.
Note that f
CLK
is dependent on the buffer’s threshold levels
as well as the resistor/capacitor tolerance (see Figure 1 ).
Schmitt-trigger threshold voltage levels can change signifi-
cantly causing the R/C oscillator’s frequency to vary greatly
from part to part.
Where accurate cutoff frequency is required, an external
clock can be used to drive the CLK R input of the LMF40.
This input is TTL logic level compatible and also presents a
very light load to the external clock source (
E
2
m
A). With
split supplies and the level shift (L. Sh) tied to system
ground, the logic level is about 2V. (See the Pin Description
for L. Sh).
8
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