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參數(shù)資料
| 型號： | LMC835N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻控制 |
| 英文描述： | LMC835 Digital Controlled Graphic Equalizer |
| 中文描述： | 1 CHANNEL(S), EQUALIZER CIRCUIT, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 474K |
| 代理商： | LMC835N |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, V
DD
b
V
SS
Allowable Input Voltage (Note 1)
18V
V
SS
b
0.3V
to V
DD
a
0.3V
b
60
§
C to
a
150
§
C
Storage Temperature, T
stg
Lead Temperature (Soldering, 10 sec), N Pkg
a
260
§
C
Lead Temperature, V Pkg
Vapor Phase (60 sec)
Infrared (15 sec)
a
215
§
C
a
220
§
C
Operating Ratings
Supply Voltage, V
DD
b
V
SS
Digital Ground (Pin 13)
5V to 16V
V
SS
to V
DD
V
SS
to V
DD
Digital Input (Pins 14, 15, 16)
Analog Input (Pins 1, 2, 3, 4, 25, 26, 27)
(Note 1)
V
SS
to V
DD
Operating Temperature, T
opr
b
40
§
C to
a
85
§
C
Electrical Characteristics
(Note 2) V
DD
e
7.5V, V
SS
eb
7.5V, A.GND
e
0V
LOGIC SECTION
Tested
Limit
(Note 3)
Design
Limit
(Note 4)
Unit
(Limit)
Symbol
Parameter
Test Conditions
Typ
I
DDL
I
SSL
I
DDH
I
SSH
Supply Current
Pins 14, 15, 16 are 0V
Pins 14, 15, 16 are 0V
Pins 14, 15, 16 are 5V
Pins 14, 15, 16 are 5V
0.01
0.01
1.3
0.9
0.5
0.5
5
5
0.5
0.5
5
5
mA (Max)
mA (Max)
mA (Max)
mA (Max)
V
IH
High-Level Input Voltage
@
Pins 14, 15, 16
1.8
2.3
2.5
V (Min)
V
IL
Low-Level Input Voltage
@
Pins 14, 15, 16
0.9
0.6
0.4
V (Max)
f
o
Clock Frequency
@
Pin 14
2000
500
500
kHz (Max)
t
w(STB)
Width of STB Input
SeeFigure 1
0.25
1
1
m
s (Min)
t
setup
Data Setup Time
SeeFigure 1
0.25
1
1
m
s (Min)
t
hold
Data Hold Time
SeeFigure 1
0.25
1
1
m
s (Min)
t
cs
Delay from Rising Edge of CLOCK
to STB
SeeFigure 1
0.25
1
1
m
s (Min)
I
IN
Input Current
@
Pins 14, 15, 16 0V
k
V
IN
k
5V
g
0.01
g
1
m
A (Max)
C
IN
Input Capacitance
@
Pins 14, 15, 16 f
e
1 MHz
5
pF
Note 1:
Pins 2, 3 and 26 have a maximum input voltage range of
g
22V for the typical application shown in Figure 7.
Note 2: Bold numbers
apply at temperature extremes. All other numbers apply at T
A
e
25
§
C, V
DD
e
7.5V, V
SS
eb
7.5V,D.GND
e
A.GND
e
0V as shown in the test
circuit, Figures 3 and 4.
Note 3:
Guaranteed and 100% production tested.
Note 4:
Guaranteed (but not 100% production tested) over the operating temperature range. These limits are not used to calculate outgoing quality levels.
Timing Diagram
TL/H/6753–3
Note:
To change the gain of the presently selected band, it is not necessary to send DATA 1 (Band Selection) each time.
FIGURE 1
3
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