參數(shù)資料
型號(hào)： LM85
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： Hardware Monitor with Integrated Fan Control
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： QSOP-24
文件頁(yè)數(shù)： 24/26頁(yè)
文件大?。?/td> 261K
代理商： LM85
Functional Description
(Continued)
23.14
30.04
38.16
47.06
61.38
94.12
1944
2523
3205
3953
5156
7906
420
420
420
420
420
420
This register is not effected when the Ready/Lock/Start/Override register Lock bit is set. After power up the default value is used
whenever the Ready/Lock/Start/Override register Start bit is cleared even though modifications to this register are possible.
4.22.2 Register 75h: Fan Spin-up Mode
Register
Address
75h
Read/
Write
R/W
Register
Name
Bit 7
(MSB)
RES
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
PWM1 SU
Default
Value
7h
Lock
Fan Spin-up Mode
RES
RES
RES
RES
PWM3 SU
PWM2 SU
U
The PWM SU bit configures the PWM spin-up mode. If PWM SU is cleared the spin-up time will terminate after time programmed
by the Fan Configuration register has elapsed. When set to a 1, the spin-up time will terminate early if the TACH reading exceeds
the Tach Minimum value or after the time programmed by the Fan Configuration register has elapsed, whichever occurs first.
This register becomes Read Only when the Ready/Lock/Start/Override register Lock bit is set.Any further attempts to write to this
register shall have no effect. After power up the default value is used whenever the Ready/Lock/Start/Override register Start bit
is cleared even though modifications to this register are possible.
4.23 Undefined Registers
Any reads to undefined registers will always return 00h. Writes to undefined registers will have no effect and will not return an
error.
5.0 XOR TEST MODE
The LM85 incorporates a XOR tree test mode. When the test mode is enabled by setting the “XEN” bit high in the Test Register
at address 6Fh via the SMBus, the part will enter XOR test mode.
Since the test mode an XOR tree, the order of the signals in the tree is not important. SMBDAT and SMBCLK are not to be
included in the test tree.
20035308
6.0 DIFFERENCES BETWEEN THE LM85BIMQ AND LM85CIMQ
It is highly recommended that
new designs use the LM85BIMQ
.
Item No.
1
2
3
Description
Voltage Monitoring Accuracy
PWM Output logic LOW loading
LSB and MSB Fan TACH value
registers (registers 28h, 29h; 2Ah,
2Bh; 2Ch, 2Dh; 2Eh, 2Fh)
LM85CIMQ
+3.5% to 0.5% of Full Scale
3mA at 0.4V
Tach value registers must be read
LSB followed by MSB. Reading the
LSB latches the MSB. For example:
if you read the LSB then the MSB,
subsequent reads of just the MSB
register will yield the old result.
Internally, the TACH result is being
updated but there is no read access
unless the LSB register is read
before an MSB.
LM85BIMQ
±
2% of Full Scale
8mA at 0.4V
Tach value registers must be read
LSB followed by MSB. Reading the
LSB latches the MSB until read.
After the MSB is read it will be
updated with a new value, without
requiring a read of the LSB register.
L
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