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參數(shù)資料
| 型號： | LM81CIMTX-32 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Serial Interface ACPI-Compatible Microprocessor System |
| 中文描述： | 串行接口ACPI的兼容微處理器系統(tǒng) |
| 文件頁數(shù)： | 27/32頁 |
| 文件大小： | 412K |
| 代理商： | LM81CIMTX-32 |
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Functional Description
(Continued)
13.7 Interrupt Mask Register 2— Address 44h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
Name
Read/
Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Description
0
1
2
3
4
5
6
7
+12Vin
Vccp2
Reserved
Reserved
Chassis Intrusion
Reserved
Reserved
RESET Enable
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
A one disables the corresponding interrupt status bit for INT interrupt.
<
7
>
= 1 in INT Mask Register 2 enables the RESET in the Configuration Register.
13.8 Reserved Register — Address 45h
Power on default –
<
7:0
>
= 00h. Read/Write for backwards compatibility.
13.9 CI Clear Register— Address 46h
Power on default –
<
7:0
>
= 0000 0000 binary
Bit
Name
Read/
Write
Read/Write
Read/Write
Description
0-6
Reserved
CI Clear
7
A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit self clears after the pulse has been output. This bit is mirrored in
Configuration Register bit 6.
www.national.com
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