參數(shù)資料
型號: LM80CIMT-5
英文描述: Single-Ended Data Acquisition System
中文描述: 單端數(shù)據(jù)采集系統(tǒng)
文件頁數(shù): 22/29頁
文件大小: 409K
代理商: LM80CIMT-5
Functional Description
(Continued)
12.0 REGISTERS AND RAM
12.1 Address Register
The main register is the ADDRESS Register. The bit designations are as follows:
Bit
Name
Read/
Write
Read/Write
Description
7-0
Address
Pointer
Address of RAM and Registers. See the tables below for detail.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Address Pointer (Power On default 00h)
A4
A7
A6
A5
A3
A2
A1
A0
12.2 Address Pointer Index (A7–A0)
Registers and RAM
A6–A0 in
Hex
Power On Value of Registers:
<
7:0
>
in Binary
0000 1000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0100
0000 0001
Configuration Register
Interrupt Status Register 1
Interrupt Status Register 2
Interrupt Mask Register 1
Interrupt Mask Register 2
Fan Divisor/RST_OUT/OS
OS
Configuration/Temperature
Resolution Register
Value RAM
00h
01h
02h
03h
04h
05h
06h
20h–3Fh
L
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