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參數(shù)資料
| 型號： | LM79CCVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Microprocessor System Hardware Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 4/31頁 |
| 文件大小： | 481K |
| 代理商： | LM79CCVF |
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Pin Description
(Continued)
Pin
Name(s)
Power
Switch
Bypass
FAN3–FAN1
SCL
SDA
RESET
Pin
Number
16
Number
of Pins
1
Type
Description
Digital Output
An active low open drain output intended to drive an external P-channel
power MOSFET for software power control.
17–19
20
21
22
3
1
1
1
Digital Input
Digital Input
Digital I/O
Digital Output
0V to +5V amplitude fan tachometer input.
Serial Bus Clock.
Serial Bus bidirectional Data.
Master Reset, 5 mA driver (open drain), active low output with a 20 ms
minimum pulse width. Available when enabeld via Bit 7 in SMI Mask
Register 2.
By default an input for the VID4 power supply readout for the system
processor (Pentium/PRO). Can be programmed as a NAND Tree
totem-pole output that provides board-level connectivity testing. Refer to
Section 11.0 on NAND Tree testing.
Internally connected to all analog circuitry. The ground reference for all
analog inputs.
Ground-referred inverting op amp input. Refer to Section 4.0 “ANALOG
INPUTS”.
Output of inverting op amp for Input 6. Refer to Section 4.0 “ANALOG
INPUTS”.
Output of inverting op amp for Input 5. Refer to Section 4.0 “ANALOG
INPUTS”.
Ground-referred inverting op amp input. Refer to Section 4.0 “ANALOG
INPUTS”.
0V to 4.096V FSR Analog Inputs.
Inputs for the power supply readouts for system microprocessor
(Pentium/PRO). This value is read in the VID/Fan Divisor Register.
Board Temperature Interrupt driven by O.S. outputs of additional
temperature sensors such as LM75. Provides internal pull-up of 10 k
.
Non-Maskable Interrupt (open source)/Interrupt Request (open drain).
The mode is selected with Bit 5 of the Configuration Register and the
output is enabled when Bit 2 of the Configuration Register is set to 1.
The default state is disabled and IRQ mode.
System Management Interrupt (open drain). This output is enabled when
Bit 1 in the Configuration Register is set to 1. The default state is
disabled.
The three lowest order bits of the 16-bit ISA Address Bus. A0
corresponds to the lowest order bit.
Chip Select input from an external decoder which decodes high order
address bits on the ISA Address Bus. This is an active low input.
VID4/NTEST
23
1
Digital
Input/Test
Output
GNDA
24
1
GROUND
IN6
25
1
Analog Input
FB6
26
1
Analog Output
FB5
27
1
Analog Output
IN5
28
1
Analog Input
IN4–IN0
VID3–VID0
29–33
34–37
5
4
Analog Input
Digital Input
BTI
38
1
Digital Input
NMI/IRQ
39
1
Digital Output
SMI
40
1
Digital Output
A2–A0
41–43
3
Digital Input
CS
44
1
Digital Input
TOTAL PINS
44
L
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