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參數(shù)資料
| 型號(hào)： | LM79CCVF |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Microprocessor System Hardware Monitor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-44 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 481K |
| 代理商： | LM79CCVF |
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Block Diagram
Pin Description
Pin
Name(s)
IORD
IOWR
SYSCLK
Pin
Number
1
2
3
Number
of Pins
1
1
1
Type
Description
Digital Input
Digital Input
Digital Input
An active low standard ISA bus I/O Read Control.
An active low standard ISA bus I/O Write Control.
The reference clock for the ISA bus. Typically ranges from 4.167 MHz to
8.33 MHz. The minimum clock frequency this input can handle is 1 Hz.
Bi-directional ISA bus Data lines. D0 corresponds to the low order bit,
with D7 the high order bit.
+5V V
CC
power. Bypass with the parallel combination of 10 μF
(electolytic or tantalum) and 0.1 μF (ceramic) bypass capacitors.
Internally connected to all digital circuitry.
Chainable SMI (System Management Interrupt) Input. This is an active
low input that propagates the SMI signal to the SMI output of the LM79
via SMI Mask Register Bit 6 and SMI enable Bit 1 of the Configuration
Register.
An active high input from an external circuit which latches a Chassis
Intrusion event. This line can go high without any clamping action
regardless of the powered state of the LM79. The LM79 provides an
internal open drain on this line, controlled by Bit 7 of NMI Mask Register
2, to provide a minimum 20 ms reset of this line.
D7–D0
4–11
8
Digital I/O
V
CC
(+5V)
12
1
POWER
GNDD
SMI__IN
13
14
1
1
GROUND
Digital Input
Chassis
Intrusion
15
1
Digital I/O
DS100036-3
L
www.national.com
3
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