參數(shù)資料
型號: LM5026SD
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: Active Clamp Current Mode PWM Controller
中文描述: 3 A SWITCHING CONTROLLER, 660 kHz SWITCHING FREQ-MAX, DSO16
封裝: 5 X 5 MM, EXPOSED PAD, LLP-16
文件頁數(shù): 2/23頁
文件大?。?/td> 936K
代理商: LM5026SD
Connection Diagram
20147902
16-Lead TSSOP, LLP
Ordering Information
Order Number
LM5026MT
LM5026MTX
LM5026SD
LM5026SDX
Package Type
TSSOP-16
TSSOP-16
LLP-16
LLP-16
NSC Package Drawing
MTC16
MTC16
SDA16A
SDA16A
Supplied As
92 Units per anti-static tube
2500 Units on Tape and Reel
Available Soon
Available Soon
Pin Descriptions
PIN
1
NAME
VIN
DESCRIPTION
Input Voltage Source
APPLICATION INFORMATION
Input to the Start-up Regulator. Operating input range is 13V to 100V
with transient capability to 105V. For power sources outside of this
range, the LM5026 can be biased directly at VCC by an external
regulator.
Line Under-Voltage Lockout An external voltage divider from the power source sets the shutdown
and standby comparator levels. When UVLO reaches the 0.4V threshold
the VCC and REF regulators are enabled. At the 1.25V threshold the SS
pin is released and the device enters the active mode.
Current Sense input for
current mode control and
current limit
after OUT_A switches high to blank leading edge transients.
Restart Timer
If cycle-by-cycle current limit is reached during any cycle, a 10uA current
is sourced to the RES pin capacitor. If the RES capacitor voltage
reaches 2.5V, the soft-start capacitor will be fully discharged and then
released with a pull-up current of 1uA. After the first output pulse at
OUT_A (when SS =1.4V), the SS pin charging current will revert back to
50 μA.
Gate Drive Overlap or
Deadtime Control
the active clamp output. An RSET resistor connected between TIME and
AGND produces in-phase OUT_A and OUT_B pulses with overlap. An
RSET resistor connected between TIME and REF produces out-of-phase
OUT_A and OUT_B pulses with deadtime.
Output of 5V Reference
Maximum output current is 10mA. Locally decouple with a 0.1μF
capacitor.
Output of the high voltage
start-up regulator. The VCC
voltage is regulated to 7.6
V.
2
UVLO
3
CS
If CS exceeds 0.5V the output pulse will be terminated, entering
cycle-by-cycle current limit. An internal switch holds CS low for 100nS
4
RES
5
TIME
An external resistor (RSET) sets either the overlap time or deadtime for
6
REF
7
VCC
If an auxiliary winding raises the voltage on this pin above the regulation
setpoint, the internal start-up regulator will shutdown, thus reducing the
IC power dissipation.
L
www.national.com
2
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