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參數(shù)資料
| 型號： | LM4931 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Audio Subsystem with Mono High Efficiency Loudspeaker and Stereo Headphone Amplifiers |
| 中文描述： | 與單聲道音頻子系統(tǒng)高效揚聲器和立體聲耳機放大器 |
| 文件頁數(shù)： | 19/47頁 |
| 文件大?。?/td> | 1640K |
| 代理商： | LM4931 |
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PLL Configuration Registers
This register is used to control the frequency divider (M divider) which sits before the PLL phase comparator, it also allows the
3 MSBs of the N_divider’s modulus input to be programmed.
See Figure 4 for further explanation.
DEFAULT CHART FOR PLL_M (05h)
DATA BIT
DEFAULT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PLL_M (05h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
4:0
Register
PLL_M
Description
Programs the PLL input divider from divide by 4 to divide by 31. It is also
possible to bypass the divider if PLL_M = 1 or divide by 2 if PLL_M = 2. Setting
PLL_M = 3 will default to divide by 4.
Programs the modulus bits [4:2] of the PLL feedback divider .
7:5
PLL_N_MOD1
This register is used to control the integer of the PLL feedback divider (fractional N divider).
DEFAULT CHART FOR PLL_N (06h)
DATA BIT
DEFAULT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PLL_N (06n) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
6:0
Register
PLL_N
Description
Programs the PLL feedback divider from divide by 4 to divide by 127, PLL_N
inputs from 0 to 3 are rounded to 4.
If set the VCO operates best at frequencies up to 100MHz, normally the VCO is
tuned for outputs around 50MHz.
7
FAST_VCO
This register is used to control the PLL output divider (P divider), it also allows the 2 LSBs of the N divider’s modulus input to be
programmed.
DEFAULT CHART FOR PLL_P (07h)
DATA BIT
DEFAULT
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
PLL_P (07h) (SET = LOGIC 1, CLEAR = LOGIC 0)
Address
3:0
Register
PLL_P
Description
Programs the PLL output divider from divide by 4 to divide by 15, PLL_P inputs
from 0 to 3 are rounded to 4. It is recommended that P = 4 to keep the VCO
around its nominal frequency of 50MHz.
Programs the PLL feedback divider modulus bits [1:0].
Programs the magnitude of the PLL dither level.
7:6
00
01
10
11
5:4
7:6
PLL_N_MOD2
DITHER_LEVEL
PLL Dither Level
32
16
48
0
The N divider is a fractional divider as such:
N = PLL_N + (PLL _NMOD/32)
If the Modulus input is zero then the N divider is simpler an integer N divider. The output from the PLL is determined by the
following formula:
Fout = (Fin*N)/(PLL_M*PLL_P)
L
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19
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相關代理商/技術參數(shù) |
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|---|---|
| LM4931_06 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Audio Subsystem with Mono High Efficiency Loudsperker and Stereo Headphone Amplifiers |
| LM4931ITL/NOPB | 功能描述:音頻放大器 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| LM4931ITLBD | 功能描述:BOARD EVALUATION LM4931ITL RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 音頻放大器 系列:Boomer® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| LM49321 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression |
| LM49321RL | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Audio Sub-System with Stereo DAC, Mono Class AB Loudspeaker Amplifier, OCL/SE Stereo Headphone Output and RF Suppression |
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