Application Information (Continued)
C
B
Ton
C
i = 0.47F
C
i = 0.33F
0.01F
110ms
80ms
0.1F
120ms
90ms
0.22F
140ms
100ms
0.47F
170ms
140ms
1.0F
240ms
210ms
In order eliminate ’clicks and pops’, all capacitors must be
discharged before turn-on. Rapidly switching V
DD may not
allow the capacitors to fully discharge, which may cause
’clicks and pops’.
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8
Load
The following are the desired operational parameters:
Power Output:
1 W
RMS
Load Impedance:
8
Input Level:
1 V
RMS
Input Impedance:
20 k
Bandwidth:
100 Hz20 kHz ± 0.25 dB
The design begins by specifying the minimum supply voltage
necessary to obtain the desired output power. One way to
find the minimum supply voltage is to use the Output Power
vs Supply Voltage curve in the Typical Performance Char-
acteristics section. Another way, using Equation (6), is to
calculate the peak output voltage necessary to achieve the
desired output power for a given load impedance. To ac-
count for the amplifier’s dropout voltage, two additional volt-
ages, based on the Dropout Voltage vs Supply Voltage in the
Typical Performance Characteristics curves, must be
added to the result obtained by Equation (6). The result is
Equation (7).
(6)
V
DD
≥ (V
OUTPEAK+(VODTOP +VODBOT))
(7)
The Output Power vs Supply Voltage graph for an 8
load
indicates a minimum supply voltage of 4.6V. This is easily
met by the commonly used 5V supply voltage. The additional
voltage creates the benefit of headroom, allowing the
LM4869 to produce peak output power in excess of 1W
without clipping or other audible distortion. The choice of
supply voltage must also not create a situation that violates
of maximum power dissipation as explained above in the
Power Dissipation section.
After satisfying the LM4869’s power dissipation require-
ments, the minimum differential gain is found using Equation
(8).
(8)
Thus, a minimum gain of 2.83 allows the LM4869’s to reach
full output swing and maintain low noise and THD+N perfor-
mance. For this example, let A
VD = 3. In the example design,
the gain will be set to 10dB (A
VD = 3.2) by applying a logic
low to GAIN 0 and a logic high to GAIN 1.
The last step in this design example is setting the amplifier’s
-3dB frequency bandwidth. To achieve the desired ±0.25dB
pass band magnitude variation limit, the low frequency re-
sponse must extend to at least one-fifth the lower bandwidth
limit and the high frequency response must extend to at least
five times the upper bandwidth limit. This extended bandwith
produces a gain variation of -0.17dB at the bandwith’s limits,
well within the ±0.25dB desired limit. The results are an
f
L = 100Hz/5 = 20Hz
(9)
and an
f
H = 20kHz x 5 = 100kHz
(10)
As mentioned in the External Components section, the inter-
nal input resistor and C
i create a high pass filter that sets the
amplifier’s lower bandpass frequency limit. Find the coupling
capacitor’s value using Equation (11).
f
-3dB = 1/2
π(20k)C
I
(11)
The result is (using the minimum R
IN resistor value to ensure
correct magnitude response at 20Hz)
1/(2
π*20k*20Hz) = 0.398F
(12)
Use a 0.39F capacitor, the closest standard value. The
product of the desired high frequency cutoff (100kHz in this
example) and the differential gain, A
VD, determines the up-
per passband response limit. With A
VD = 3.2 and fH =
100kHz, the closed-loop gain bandwidth product (GBWP) is
320kHz. This is less than the LM4869’s 3.5MHz GBWP. With
this margin, the amplifier can be used in designs that require
more differential gain while avoiding performance-restricting
bandwidth limitations.
LM4869
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