參數(shù)資料
型號: LM4550BVHX/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 消費(fèi)家電
英文描述: LM4550B AC '97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound; Package: LQFP; No of Pins: 48; Qty per Container: 1000/Reel
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
文件頁數(shù): 18/31頁
文件大?。?/td> 998K
代理商: LM4550BVHX/NOPB
Register Descriptions (Continued)
BIT#
BIT
Function: Powerdown
15
EAPD
External Amplifier PowerDown
*0 = Set EAPD Pin to 0 (pin 47)
Default:000Fh if ready; otherwise 000Xh
EXTENDED AUDIO ID REGISTER (28h)
This read-only (X201h) register identifies which AC ’97 Ex-
tended Audio features are supported. The LM4550B features
AMAP (Slot/DAC mappings based on Codec Identity), VRA
(Variable Rate Audio) and ID1, ID0, the Codec Identity bits
used to support multi-codec systems. AMAP is indicated by
a "1" in bit 9, VRA is indicated by a "1" in bit 0. The two
MSBs, ID1 and ID0, show the current Codec Identity as
defined by the Identity pins ID1#, ID0#. Note that the exter-
nal logic connections to ID1#, ID0# (pins 46 and 45) are
inverse in polarity to the value of the Codec Identity (ID1,
ID0) held in bits D15, D14. The AMAP Slot/DAC mappings
are given in Table 1 in the Multiple Codec section. Codec
mode selections are shown in the table below.
Pin 46
(ID1#)
Pin 45
(ID0#)
D15,28h
(ID1)
D14,28h
(ID0)
Codec Identity
Mode
NC/DV
DD
NC/DV
DD
0
Primary
NC/DV
DD
GND
0
1
Secondary 1
GND
NC/DV
DD
1
0
Secondary 2
GND
1
Secondary 3
EXTENDED AUDIO STATUS/CONTROL REGISTER
(2Ah)
This read/write register provides status and control of the
variable sample rate capabilities in the LM4550B. Setting the
LSB of this register to "1" enables Variable Rate Audio (VRA)
mode and allows DAC and ADC sample rates to be pro-
grammed via registers 2Ch and 32h respectively.
BIT
Function
VRA
*0 = VRA off (Frame-rate sampling)
1 = VRA on
Default: 0000h
SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)
These read/write registers are used to set the sample rate
for the left and right channels of the DAC (PCM DAC Rate,
2Ch) and the ADC (PCM ADC Rate, 32h). When Variable
Rate Audio is enabled via bit 0 of the Extended Audio
Control/Status register (2Ah), the sample rates can be pro-
grammed, in 1 Hz increments, to be any value from 4 kHz to
48 kHz. The value required is the hexadecimal representa-
tion of the desired sample rate, e.g. 8000
10 = 1F40h. Below
is a list of the most common sample rates and the corre-
sponding register (hex) values.
Common Sample Rates
SR15:SR0
Sample Rate (Hz)
1F40h
8000
2B11h
11025
3E80h
16000
5622h
22050
AC44h
44100
*BB80h
*48000
CHAIN-IN CONTROL REGISTER (74h)
This read/write register is only needed when using the Chain
In feature. This feature goes beyond the AC ’97 specification
and is not required for standard AC Link operation. The two
LSBs of this register default to the Codec Identity (ID1, ID0)
after reset. This default state corresponds to standard AC
Link operation where the output of codec pin 8 (SDATA_IN)
carries the AC Link Input Frames back to the controller from
the codec.
If the two LSBs differ from the Codec Identity (register 28h
describes the Codec Identity), then the signal present at CIN
(pin 48) is switched through to the SDATA_IN (pin 8) output.
In this fashion, Secondary codecs can be chained together
by connecting one codec’s SDATA_IN pin to the next co-
dec’s CIN pin. This has the end result of only requiring a
single SDATA_IN pin at the controller rather than the stan-
LM4550B
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