參數(shù)資料
型號： LM4550BVHX/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費家電
英文描述： LM4550B AC '97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound; Package: LQFP; No of Pins: 48; Qty per Container: 1000/Reel
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
文件頁數(shù)： 11/31頁
文件大?。?/td> 998K
代理商： LM4550BVHX/NOPB
AC Link Serial Interface Protocol
(Continued)
The LM4550B expects to receive data MSB first, in an MSB
justified format.
SDATA_OUT: Slot 0 – Tag Phase
The first bit of Slot 0 is designated the "Valid Frame" bit. If
this bit is 1, it indicates that the current Output Frame con-
tains at least one slot of valid data and the LM4550B will
check further tag bits for valid data in the expected Data
Slots. With the codec in Primary mode, a controller will
indicate valid data in a slot by setting the associated tag bit
equal to 1. Since it is a two channel codec the LM4550B can
only receive data from four slots in a given frame and so only
checks the valid-data bits for 4 slots. In Primary mode these
tag bits are for: slot 1 (Command Address), slot 2 (Command
Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data
for right DAC).
The last two bits in the Tag contain the Codec ID used to
select the target codec to receive the frame in multiple codec
systems. When the frame is being sent to a codec in one of
the Secondary modes the controller does not use bits 14 and
13 to indicate valid Command Address and Data in slots 1
and 2. Instead, this role is performed by the Codec ID bits –
operation of the Extended AC Link assumes that the control-
ler would not access a secondary codec unless it was pro-
viding valid Command Address and/or Data. When in one of
the secondary modes the LM4550B only checks the tag bits
for the Codec ID and for valid data in the two audio data
slots: slots3&4for Secondary mode 1, slots7&8for mode
2 and slots6&9for mode 3.
When sending an Output Frame to a Secondary mode co-
dec, a controller should set tag bits 14 and 13 to zero.
SLOT 0, OUTPUT FRAME
Bit
Description
Comment
15
Valid Frame
1 = Valid data in at least one
slot.
14
Control register
address
1 = Valid Control Address in
Slot 1 (Primary codec
only)
13
Control register
data
1 = Valid Control Data in Slot
2 (Primary codec only)
Bit
Description
Comment
12
Left DAC data
in Slot 3
1 = Valid PCM Data in Slot 3
(Primary & Secondary 1
modes; Left Channel
audio)
11
Right DAC data
in Slot 4
1 = Valid PCM Data in Slot 4
(Primary & Secondary 1
modes; Right Channel
audio)
10
Not Used
Controller should stuff this slot
with “0”s
9
Left DAC data
in Slot 6
1 = Valid PCM Data in Slot 6
(Secondary 3 mode;
Center Channel audio)
8
Left DAC data
in Slot 7
1 = Valid PCM Data in Slot 7
(Secondary 2 mode; Left
Surround Channel audio)
7
Right DAC data
in Slot 8
1 = Valid PCM Data in Slot 8
(Secondary 2 mode;
Right Surround Channel
audio)
6
Right DAC data
in Slot 9
1 = Valid PCM Data in Slot 9
(Secondary 3 mode; LFE
Channel audio)
5:2
Not Used
Controller should stuff these
slots with “0”s
1,0
Codec ID
(ID1, ID0)
The Codec ID (Table 1) selects
the target codec in a
multi-codec system to receive
the control address and data
carried in the Output Frame
SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of
a target register in the LM4550B and whether the access
operation is a register read or register write. The MSB of slot
1 (bit 19) is set to 1 to indicate that the current access
operation is ’read’. Bits 18 through 12 are used to specify the
7-bit register address of the read or write operation. The
least significant twelve bits are reserved and should be
stuffed with zeros by the AC ’97 controller.
SLOT 1, OUTPUT FRAME
Bits
Description
Comment
19
Read/Write
1 = Read
0 = Write
18:12
Register
Address
Identifies the Status/Command
register for read/write
11:0
Reserved
Controller should set to "0"
SDATA_OUT: Slot 2 – Control Data
Slot 2 is used to transmit 16-bit control data to the LM4550B
when the access operation is ’write’. The least significant
four bits should be stuffed with zeros by the AC ’97 controller.
If the access operation is a register read, the entire slot, bits
19 through 0 should be stuffed with zeros.
20123705
FIGURE 5. Start of AC Link Output Frame
LM4550B
www.national.com
19
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相關代理商/技術參數(shù)
參數(shù)描述
LM4550C-46 WAF 制造商:Texas Instruments 功能描述:
LM4550VH 功能描述:IC AC '97 CODEC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
LM4550VH WAF 制造商:Texas Instruments 功能描述:
LM4550VH/NOPB 功能描述:IC AC '97 CODEC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
LM4550VHX 制造商:Rochester Electronics LLC 功能描述:AC '97 REV 2.1 CODEC - Bulk
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