AC Link Serial Interface Protocol
(Continued)
checks the valid-data bits for 4 slots. In Primary mode these
tag bits are for: slot 1 (Command Address), slot 2 (Command
Data), slot 3 (PCM data for left DAC) and slot 4 (PCM data
for right DAC).
The last two bits in the Tag contain the Codec ID used to
select the target codec to receive the frame in multiple codec
systems. When the frame is being sent to a codec in one of
the Secondary modes the controller does not use bits 14 and
13 to indicate valid Command Address and Data in slots 1
and 2. Instead, this role is performed by the Codec ID bits –
operation of the Extended AC Link assumes that the control-
ler would not access a secondary codec unless it was pro-
viding valid Command Address and/or Data. When in one of
the secondary modes the LM4548A only checks the tag bits
for the Codec ID and for valid data in the two audio data slots
3&4.
When sending an Output Frame to a Secondary mode co-
dec, a controller should set tag bits 14 and 13 to zero.
SLOT 0, OUTPUT FRAME
Bit
Description
Comment
15
Valid Frame
1 = Valid data in at least one
slot.
14
Control register
address
1 = Valid Control Address in
Slot 1 (Primary codec
only)
13
Control register
data
1 = Valid Control Data in Slot
2 (Primary codec only)
12
Left DAC data
in Slot 3
1 = Valid PCM Data in Slot 3
(Primary & all Secondary
modes)
11
Right DAC data
in Slot 4
1 = Valid PCM Data in Slot 4
(Primary & all Secondary
modes)
10:2
Not Used
Controller should stuff these
slots with “0”s
Bit
Description
Comment
1,0
Codec ID
(ID1, ID0)
The codec ID is used in a
multi-codec system to identify
the target Secondary codec for
the Control Register address
and/or data sent in the Output
Frame
SDATA_OUT: Slot 1 – Read/Write, Control Address
Slot 1 is used by a controller to indicate both the address of
a target register in the LM4548A and whether the access
operation is a register read or register write. The MSB of slot
1 (bit 19) is set to 1 to indicate that the current access
operation is ’read’. Bits 18 through 12 are used to specify the
7-bit register address of the read or write operation. The
least significant twelve bits are reserved and should be
stuffed with zeros by the AC ’97 controller.
SLOT 1, OUTPUT FRAME
Bits
Description
Comment
19
Read/Write
1 = Read
0 = Write
18:12
Register
Address
Identifies the Status/Command
register for read/write
11:0
Reserved
Controller should set to "0"
SDATA_OUT: Slot 2 – Control Data
Slot 2 is used to transmit 16-bit control data to the LM4548A
when the access operation is ’write’. The least significant
four bits should be stuffed with zeros by the AC ’97 controller.
If the access operation is a register read, the entire slot, bits
19 through 0 should be stuffed with zeros.
SLOT 2, OUTPUT FRAME
Bits
Description
Comment
19:4
Control
Register Write
Data
Controller should stuff with
zeros if operation is “read”
3:0
Reserved
Set to "0"
SDATA_OUT: Slots3&4 – PCM Playback Left/Right
Channels
Slots 3 and 4 are 20-bit fields used to transmit PCM data to
the left and right channels of the stereo DAC for all codec
Primary and Secondary modes. Any unused bits should be
stuffed with zeros. The LM4548A DACs have 18-bit resolu-
tion and will therefore use the 18 MSBs of the 20-bit PCM
data (MSB justified).
SLOTS3&4, OUTPUT FRAME
Bits
Description
Comment
19:0
PCM DAC Data
(Left /Right
Channels)
Slots used to stream data to
DACs for all Primary or
Secondary modes.
Set unused bits to "0"
20030005
FIGURE 5. Start of AC Link Output Frame
LM4548A
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