參數(shù)資料
型號： LM4546BVH/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 消費家電
英文描述： LM4550 AC '97 Rev 2.1 Multi-Channel Audio Codec with Stereo Headphone Amplifier, Sample Rate Conversion and National 3D Sound; Package: LQFP; No of Pins: 48; Qty per Container: 250/Tray
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： 7 X 7 MM, 1.40 MM HEIGHT, LQFP-48
文件頁數(shù)： 18/27頁
文件大小： 903K
代理商： LM4546BVH/NOPB
Multiple Codecs (Continued)
The Identity control pins, ID1, ID0 (pins 46 and 45) are
internally pulled up to DV
DD. The Codec may therefore be
configured as ’Primary’ either by leaving ID1, ID0 open (NC)
or by strapping them externally to DV
DD (Digital supply).
The difference between Primary and Secondary codec
modes is in their timing source and in the Tag Bit handling in
Output Frames for Command/Status register access. For a
timing source, a Primary codec divides down by 2 the fre-
quency of the signal on XTAL_IN and also generates this as
the BIT_CLK output for the use of the controller and any
Secondary codecs. Secondary codecs use BIT_CLK as an
input and as their timing source and do not use XTAL_IN or
XTAL_OUT. The use of Tag Bits is described below.
SECONDARY CODEC REGISTER ACCESS
For Secondary Codec access, the controller must set the tag
bits for Command Address and Data in the Output Frame as
invalid (i.e. equal to 0). The Command Address and Data tag
bits are in slot 0, bits 14 and 13 and Output Frames are
those in the SDATA_OUT signal from controller to codec.
The controller must also place the non-zero value (01, 10, or
11) corresponding to the Identity (ID1, ID0) of the target
Secondary Codec into the Codec ID field (slot 0, bits 1 and 0)
in that same Output Frame. The value set in the Codec ID
field determines which of the three possible Secondary Co-
decs is accessed. Unlike a Primary Codec, a Secondary
Codec will disregard the Command Address and Data tag
bits when there is a match between the 2-bit Codec ID value
(slot 0, bits 1 and 0) and the Codec Identity (ID1, ID0).
Instead it uses the Codec-ID/Identity match to indicate that
the Command Address in slot 1 and (if a “write”) the Com-
mand Data in slot 2 are valid.
When reading from a Secondary Codec, the controller must
send the correct Codec ID bits (i.e. the target Codec Identity
in slot 0, bits 1 and 0) along with the read-request bit (slot 1,
bit 19) and target register address (slot 1, bits 18 – 12). To
write to a Secondary Codec, a controller must send the
correct Codec ID bits when slot 1 contains a valid target
register address and “write” indicator bit and slot 2 contains
valid target register data. A write operation is only valid if the
register address and data are both valid and sent within the
same frame. When accessing the Primary Codec, the Codec
ID bits are cleared and the tag bits 14 and 13 resume their
role indicating the validity of Command Address and Data in
slots 1 and 2.
The use of the tag bits in Input Frames (carried by the
SDATA_IN signal) is the same for Primary and Secondary
Codecs.
The Codec Identity is determined by the input pins ID1#,
ID0# (pins 46 and 45) and can be read as the value of the
ID1, ID0 bits (D15, D14) in the Extended Audio ID register,
28h of the target codec.
Slots in the AC Link Output Frame are always mapped to
carry data to the left DAC channel in slot 3 and data to the
right DAC channel in slot 4. Similarly, slots in AC Link Input
Frames are always mapped such that PCM data from the left
ADC channel is carried by slot 3 and PCM data from the right
ADC channel by slot 4. Output Frames are those carried by
the SDATA_OUT signal from the controller to the codec
while Input Frames are those carried by the SDATA_IN
signal from the codec to the controller.
SLOT 0: TAG bits in Output Frames (controller to codec)
Bit 15
14
13
12
11
10
987654321
0
Valid
Frame
Slot 1
Valid
Slot 2
Valid
Slot 3
Valid
Slot 4
Valid
XXXXXXXXX
ID1
ID0
Extended Audio ID register (28h): Support for Multiple Codecs
Reg
Name
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
28h
Extended
Audio ID
ID1
ID0
XXXXXXXXXXXXX
VRA
X001h
LM4546B
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LM4546BVHX 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
LM4546BVHX/NOPB 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
LM4546VH 制造商:Texas Instruments 功能描述:SPECIALTY CONSUMER CIRCUIT, PQFP48
LM4547VH 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Soundcard Circuits
LM4548 制造商:NSC 制造商全稱:National Semiconductor 功能描述:AC ’97 Rev 2 Codec with Sample Rate Conversion and National 3D Sound
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