參數(shù)資料
型號(hào)： LM3310
廠商： National Semiconductor Corporation
英文描述： Step-up PWM DC/DC Converter with Integrated Op-Amp and Gate Pulse Modulation Switch
中文描述： 升壓PWM直流/直流轉(zhuǎn)換器集成的運(yùn)算放大器和脈沖調(diào)制開(kāi)關(guān)門
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 1668K
代理商： LM3310
Operation
(Continued)
does not begin switching until the input voltage reaches the
UVP On threshold. If the input voltage is present and the
shutdown pin is pulled high the UVP circuitry will prevent the
device from switching if the input voltage present is lower
than the UVP On threshold. During normal operation the
UVP circuitry will disable the device if the input voltage falls
below the UVP Off threshold for any reason. In this case the
device will not turn back on until the UVP On threshold
voltage is exceeded.
OPERATIONAL AMPLIFIER
Compensation:
The architecture used for the amplifier in the LM3310 re-
quires external compensation on the output. Depending on
the equivalent resistive and capacitive distributed load of the
TFT-LCD panel, external components at the amplifier out-
puts may or may not be necessary. If the capacitance pre-
sented by the load is equal to or greater than an equivalent
distibutive load of 50
in series with 4.7nF no external
components are needed as the TFT-LCD panel will act as
compensation itself. Distributed resistive and capacitive
loads enhance stability and increase performance of the
amplifiers. If the capacitance and resistance presented by
the load is less than 50
in series with 4.7nF, external
components will be required as the load itself will not ensure
stability. No external compensation in this case will lead to
oscillation of the amplifier and an increase in power con-
sumption. A good choice for compensation in this case is to
add a 50
in series with a 4.7nF capacitor from the output of
the amplifier to ground. This allows for driving zero to infinite
capacitance loads with no oscillations, minimal overshoot,
and a higher slew rate than using a single large capacitor.
The high phase margin created by the external compensa-
tion will guarantee stability and good performance for all
conditions.
Layout and Filtering considerations:
When the power supply for the amplifiers (AV
) is con-
nected to the output of the switching regulator, the output
ripple of the regulator will produce ripple at the output of the
amplifiers. This can be minimized by directly bypassing the
AV
pin to ground with a low ESR ceramic capacitor. For
best noise reduction a resistor on the order of 5
to 20
from the supply being used to theAV
pin will create and RC
filter and give you a cleaner supply to the amplifier. The
bypass capacitor should be placed as close to the AV
IN
pin
as possible and connected directly to the AGND plane.
For best noise immunity all bias and feedback resistors
should be in the low k
range due to the high input imped-
ance of the amplifier. It is good practice to use a small
capacitance at the high impedance input terminals as well to
reduce noise susceptibility. All resistors and capacitors
should be placed as close to the input pins as possible.
Special care should also be taken in routing of the PCB
traces. All traces should be as short and direct as possible.
The output pin trace must never be routed near any trace
going to the positive input. If this happens cross talk from the
output trace to the positive input trace will cause the circuit to
oscillate.
The op-amp is not a three terminal device it has 5 terminals:
positive voltage power pin, AGND, positive input, negative
input, and the output. The op-amp "routes" current from the
power input pin and AGND to the output pin. So in effect an
opamp has not two inputs but four, all of which must be kept
noise free relative to the external circuits which are being
driven by the op-amp. The current from the power pins goes
through the output pin and into the load and feedback loop.
The current exiting the load and feedback loops then must
have a return path back to the op-amp power supply pins.
Ideally this return path must follow the same path as the
output pin trace to the load. Any deviation that makes the
loop area larger between the output current path and the
return current path adds to the probability of noise pick up.
GATE PULSE MODULATION
The Gate Pulse Modulation (GPM) block is designed to
provide a modulated voltage to the gate driver circuitry of a
TFT LCD display. Operation is best understood by referring
to the GPM block diagram in the
Block Diagrams
section, the
drawing in
Figure 2
and the transient waveforms in
Figure 3
and
Figure 4
.
There are two control signals in the GPM block, VDPM and
VFLK. VDPM is the enable pin for the GPM block. If VDPM
is high, the GPM block is active and will respond to the VFLK
drive signal from the timing controller. However, if VDPM is
low, the GPM block will be disabled and both PMOS
switches P2 and P3 will be turned off. The VGHM node will
be discharged through a 1k
resistor and the NMOS switch
N2.
When VDPM is high, typical waveforms for the GPM block
can be seen in
Figure 2
. The pin VGH is typically driven by
a 2x or 3x charge pump. In most cases, the 2x or 3x charge
pump is a discrete solution driven from the SW pin and the
output of the boost switching regulator. When VFLK is high,
the PMOS switch P2 is turned on and the PMOS switch P3
is turned off. With P2 on, the VGHM pin is pulled to the same
voltage applied to the VGH pin. This provides a high gate
drive voltage, VGHM
MAX
, and can source current to the gate
drive circuitry. When VFLK is high, NMOS switch N3 is on
which discharges the capacitor CE.
When VFLK is low, the NMOS switch N3 is turned off which
allows current to charge the C
capacitor. This creates a
delay, t
DELAY
, given by the following equations:
t
DELAY
)
1.265V(C
E
+ 7pF)/I
CE
When the voltage on CE reaches about 1.265V and the
VFLK signal is low, the PMOS switch P2 will turn off and the
PMOS switch P3 will turn on connecting resistor R3 to the
VGHM pin through P3. This will discharge the voltage at
VGHM at some rate determined by R3 creating a slope, M
R
,
as shown in
Figure 2
. The VGHM pin is no longer a current
source, it is now sinking current from the gate drive circuitry.
20133384
FIGURE 2.
L
www.national.com
15
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LM3310_07 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Step-Up PWM DC/DC Converter with Integrated Op-Amp and Gate Pulse Modulation Switch
LM3310SQ 功能描述:DC/DC 開(kāi)關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
LM3310SQ/NOPB 功能描述:DC/DC 開(kāi)關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
LM3310SQX 功能描述:DC/DC 開(kāi)關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
LM3310SQX/NOPB 功能描述:DC/DC 開(kāi)關(guān)控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開(kāi)關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
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