參數(shù)資料
型號: LM2696MXA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: 3A, Constant On Time Buck Regulator
中文描述: 6.4 A SWITCHING REGULATOR, 500 kHz SWITCHING FREQ-MAX, PDSO16
封裝: TSSOP-16
文件頁數(shù): 15/19頁
文件大?。?/td> 833K
代理商: LM2696MXA
Application Information
(Continued)
LINE REGULATION
The LM2696 regulates to the lowest point of the output
voltage (V
L
in
Figure 8
). This is to say that the output voltage
may be represented by a waveform that is some average
voltage with ripple. The LM2696 will regulate to the trough of
the ripple.
The output voltage is given by the following relationship:
as discussed in the Feedback Resistor section of this docu-
ment.
TRANSIENT RESPONSE
Constant on-time architectures have inherently excellent
transient line and load response. This is because the control
loop is extremely fast. Any change in the line or load condi-
tions will result in a nearly instantaneous response in the
PWM off time.
If one considers the switcher response to be nearly cycle-
by-cycle, and amount of energy contained in a single PWM
pulse, there will be very little change in the output for a given
change in the line or load.
EFFICIENCY
The constant on-time architecture features high efficiency
even at light loads. The ability to achieve high efficiency at
light loads is due to the fact that the off-time will become
necessarily long at light loads. Having extended the off-time,
there is little mechanism for loss during this interval.
The efficiency is easily estimated using the following rela-
tionships:
Power loss due to FET:
P
FET
= P
C
+ P
GC
+ P
SW
Where:
P
C
= D
(I
OUT2
R
DS_ON
)
P
GC
= AV
IN
+ V
GS
Q
GS
f
SW
P
SW
= 0.5
V
IN
· I
OUT
(t
r
+ t
f
)
f
SW
Typical values are:
R
DS_ON
= 130 m
V
GS
= 4V
Q
GS
= 13.3 nC
t
r
= 3.8 ns
t
f
= 4.5 ns
Power loss due to catch diode:
P
D
= (1-D)
(I
OUT
V
f
)
Power loss due to DCR and ESR:
P
DCR
= I
OUT2
R
DCR
P
ESR_OUTPUT
= I
RIPPLE2
/
12
R
ESR_OUTPUT
P
ESR_INPUT
= I
OUT2
(D(1-D))
R
ESR_INPUT
Power loss due to Controller:
P
CONT
= V
IN
I
Q
I
Q
is typically 1.3 mA
The efficiency may be calculated as shown below:
Total power loss = P
FET
+ P
D
+ P
DCR
+ P
ESR_OUTPUT
+
P
ESR_INPUT
+ P
CONT
Power Out = I
OUT
V
OUT
20153446
FIGURE 7. Parasitic Tank Circuit at the Switchpin
20153447
FIGURE 8. Average Output Voltage and Regulation Point
L
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15
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