![](http://datasheet.mmic.net.cn/230000/LM2619MTC_datasheet_15592853/LM2619MTC_10.png)
Device Information
(Continued)
tor and load. The inductor limits the current to a ramp with a
slope of (V
–V
)/L, by storing energy in a magnetic field.
During the second part of each cycle, the controller turns the
PFET switch off, blocking current flow from the input, and
then turns the NFET synchronous rectifier on. In response,
the inductor’s magnetic field collapses, generating a voltage
that forces current from ground through the synchronous
rectifier to the output filter capacitor and load. As the stored
energy is transferred back into the circuit and depleted, the
inductor current ramps down with a slope of V
/L. If the
inductor current reaches zero before the next cycle, the
synchronous rectifier is turned off to prevent current reversal.
The output filter capacitor stores charge when the inductor
current is high, and releases it when low, smoothing the
voltage across the load.
The output voltage is regulated by modulating the PFET
switch on time to control the average current sent to the load.
The effect is identical to sending a duty-cycle modulated
rectangular wave formed by the switch and synchronous
rectifier at SW to a low-pass filter formed by the inductor and
output filter capacitor. The output voltage is equal to the
average voltage at the SW pin.
PWM OPERATION
While in PWM (Pulse Width Modulation) mode, the output
voltage is regulated by switching at a constant frequency
and then modulating the energy per cycle to control power to
the load. Energy per cycle is set by modulating the PFET
switch on-time pulse-width to control the peak inductor cur-
rent. This is done by comparing the signal from the current-
sense amplifier with a slope compensated error signal from
the voltage-feedback error amplifier. At the beginning of
each cycle, the clock turns on the PFET switch, causing the
inductor current to ramp up. When the current sense signal
ramps past the error amplifier signal, the PWM comparator
turns off the PFET switch and turns on the NFET synchro-
nous rectifier, ending the first part of the cycle. If an increase
in load pulls the output voltage down, the error amplifier
output increases, which allows the inductor current to ramp
higher before the comparator turns off the PFET. This in-
creases the average current sent to the output and adjusts
for the increase in the load.
Before going to the PWM comparator, the error signal is
summed with a slope compensation ramp from the oscillator
for stability of the current feedback loop. During the second
part of the cycle, a zero crossing detector turns off the NFET
synchronous rectifier if the inductor current ramps to zero.
The minimum on time of the PFET in PWM mode is about
200ns.
20065107
FIGURE 5. Simplified Functional Diagram
L
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PrintDate=2003/08/20 PrintTime=18:54:05 801627bc ds200651_p Rev. No. 1.25
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