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參數資料
| 型號： | LM2502SQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| 中文描述： | LINE TRANSCEIVER, QCC40 |
| 封裝： | 5 X 5 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, LLP-40 |
| 文件頁數： | 20/27頁 |
| 文件大?。?/td> | 1089K |
| 代理商： | LM2502SQ |
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Functional Description
(Continued)
TABLE 8. READ—Intel μP Interface Parameters
No.
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
Parameter
Min
20
Typ
Max
Units
ns
ns
MC Cycles
MC Cycles
MC Cycles
MC Cycles
ns
ns
MC Cycles
MC Cycles
ns
ns
ns
MC Cycles
ns
MC Cycles
MasterIN
MasterIN
Master
Slave
Slave
Slave
Slave
Slave
Slave
Master
Master
MasterOUT
MasterOUT
MasterOUT
MasterOUT
MasterOUT
Set Up Time (A/D, RD
*
) and Data On Time
Hold Time (A/D, RD
*
) and Data Off Time
Master Latency
Slave Latency
Read* Delay
Read Low Pulse Width
Data Set Up Time
Data Hold Time
Slave Read Latency
MST Read Latency and INTR Delay
Data Delay
Data Valid after Strobe
RD* active pulse width
INTR De-assert
Recovery Time
INTR Response, (Note 5)
15
5
6
1
6
5
15
4
12
18.6
15
20
5
5
0
LM2502 Features and Operation
POWER SUPPLIES
The V
and V
(MPL and PLL) must be connected to
the same potential between 2.9V and 3.3V. V
DDIO
powers
the logic interface and may be powered between 1.7 and
3.3V to be compatible with a wide range of host and target
devices. V
DDIO
should not be powered up without V
DDcore
/
V
DDA
applied as V
DDcore
biases the IO ring. During power
up, all rails should power up at the same time, or V
DDcore
/
V
DDA
should lead.
POWER DOWN/OFF
The Master and the Slave provide a PD* pin to save power
when the link is not needed. A Low on this pin will power
down the entire device and turn off the line current to MD0,
MD1, and MC.
During power up, the PD* inputs should be held LOW and
released once power is stable and within specification. The
Slave PD* may be released first or at the same time as the
Master’s PD
*
pin. CLK (Master) should be applied prior to
releasing PD*. If the Powerdown state is not required, the
PD
*
pins maybe connected to V
, however V
should
power up smooth through the logic threshold region.
In Powerdown (PD
*
= GND) the following outputs are driven
to:
Master:
INTR = L
Slave
depends on mode configuration - see
Table 9
.
TABLE 9. SLV Output in Powerdown
Pin
SLV
i80
H
L
L
H
L
H
H
SLV
m68
H
L
L
H
H
H
H
AD
Data[n]
CLK
CS1
*
CS2
*
MF0
MF1
BYPASS RECOMMENDATIONS
Bypass capacitors should be placed near the power supply
pins of the device. Use high frequency ceramic (surface
mount recommended) 0.1 μF capacitors. A 2.2 to 4.7 μF
Tantalum capacitor is recommended near the Master (SER)
V
DDA
pin for PLL bypass. Connect bypass capacitors with
wide traces and use dual or larger via to reduce resistance
and inductance of the feeds. Utilizing a thin spacing between
power and ground planes will provide good high frequency
bypass above the frequency range where most typical sur-
face mount capacitors are less effective. To gain the maxi-
mum benefit from this, low inductance feed points are impor-
tant. Also, adjacent signal layers can be filled to create
additional capacitance. Minimize loops in the ground returns
also for improved signal fidelity and lowest emissions.
UN-USED/OPEN PINS
Unused inputs must be tied to the proper input level—do not
float them. Unused outputs should be left open to minimize
power dissipation.
PHASE-LOCKED LOOP
When the LM2502 is configured as a Master, a PLL is
enabled to generate the serial link clock. The Phase-locked
loop system generates the serial data clock at several mul-
tiples of the input clock. The PLL operates with an input clock
L
www.national.com
20
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LM2502SQ/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| LM2502SQX/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數據速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數量:1 輸出端數量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| LM25037 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual-Mode PWM Controller With Alternating Outputs |
| LM25037EVAL | 功能描述:電源管理IC開發(fā)工具 LM25037 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| LM25037EVAL/NOPB | 功能描述:電源管理IC開發(fā)工具 LM25037 Eval Brd RoHS:否 制造商:Maxim Integrated 產品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
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