參數(shù)資料
型號： LM2502SQ
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer
中文描述： LINE TRANSCEIVER, QCC40
封裝： 5 X 5 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, LEAD FREE, LLP-40
文件頁數(shù)： 12/27頁
文件大?。?/td> 1089K
代理商： LM2502SQ
Functional Description
(Continued)
WRITE TRANSACTION
The WRITE transaction consists of two MC edges of control
information followed by 8 MC edges of write data. Since
WRITE transactions transfer information on both edges of
MC it takes 5 MC cycles to complete a write transaction. The
MD0 line carries the Start bit (High), the A/D (Address/Data)
bit and then the data payload of 8 bits (D0–7). The MD1 line
carries the R/W* bit (Read/Write*), the CS1/2 bit and then
the data payload of 8 bits (D8–15). The data payload is sent
least significant bit (LSB) first. The CS1/2 bit denotes which
Chipset pin was active. CS1/2 = HIGH designates that CS1*
is active (Low). CS1/2 = LOW designates that CS2* is active
(Low). CS1* and CS2* LOW is not allowed.
READ TRANSACTION
The READ transaction is variable in length. It consists of four
sections.
In the first section the Master sends a READ_Command to
the slave. This command is sent in a single MC cycle (2
edges) and uses a similar format to the 1st cycle of the
WRITE transaction. The MD0 line carries the Start bit (High)
and the A/D (Address/Data) bit. The MD1 line carries the
R/W* bit (High for reads) and the CS1/2 bit.
In the second section (TA’) the MD lines are turned around,
such that the Master becomes the receiver and Slave be-
comes the transmitter. The Slave must drive the MD lines
low by the 14th clock edge. It may then idle the line at the
Logic Low state or drive the line High to indicate that read
data transmission is starting. This ensures that the MD lines
are a stable LOW state and that the Low-to-High transition of
the “Start” bit is seen by the Master.
The third section consists of the transfer of the read data
from the Slave to the Master. Note that the READ_Data
operates on single-edge strobing (Rising Edge ONLY).
Therefore the back channel data signaling rate is
1
2
of the
forward channel (Master-to-Slave direction). When the Slave
is ready to transmit data back to the Master it drives the MD
lines High to indicate start of read data, followed by 8 MC
cycles of the actual read data payload. As in the WRITE
command MD0 carries D0–7 and MD1 carries D8–5. The
Master monitors for the start bit transition (Low to High) and
selects the best strobe to sample the incoming data on. This
is done to account for the round trip delay of the interconnect
and application data rate.
The Master detects the location of the START bit on MD0
and selects the best strobe for data capture. Skew between
the data lines is constrained tighter in the Master-to-Slave
direction (Write) than in the Read direction due to the data
rate difference. The Master uses its internal clock (multiple
phases) to latch the data.
The fourth and final section (TA”) occurs after the read data
has been transferred from the Slave to the Master. In the
20093307
FIGURE 8. Dual MD Link WRITE Transaction
20093308
FIGURE 9. READ_Command and TA’
L
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參數(shù)描述
LM2502SQ/NOPB 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
LM2502SQX/NOPB 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64
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