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參數(shù)資料
| 型號： | LM2502 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| 中文描述： | 移動像素鏈路（MPL）的顯示接口串行器和解串 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大小： | 1089K |
| 代理商： | LM2502 |
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Application Information
(Continued)
RGB565 APPLICATION
The LM2502 chipset may also be configured for a RGB565
application. This is also known as a "buffer-less" or "dumb"
display application. In this configuration 16 color bits (R[4:0],
G[5:0], B[4:0]), Pixel Clock (PCLK) and two control bits (VS
and HS) are supported. An external invertor is also required.
To configure for the RGB565 mode, the i80 mode must be
selected. The Pixel clock should be connected to both the
CLK input and the WR* pins on the Master. The PLL_CON
pins should be configured for a 6X mode, as it takes 5 MC
cycles to transfer the RGB data, and the 6X setting will
provide a 50% output PCLK from the Slave device. The 50%
duty cycle PCLK is created by the WR* signal which pulses
low for 3 MC cycles and is high for 2 MC cycles and an idle
MC cycle. See
Figure 20
for details. Support is provided for
PCLKs in the 3 to 25 MHz range. PLLCON setting of X8 is
also possible, however, the Slave output PCLK (WR*) will
have some duty cycle distortion (37.5%).
Slower PCLK rates maybe supported if a higher frequency
multiple of the PCLK is available. For example, if a 2MHz
PCLK is required, then a 6MHz CLK (freq locked, not phase)
may be applied to the MST CLK input and the 2MHz PCLK
to the MST WR* signal input. The PLLCON setting should be
selected as 2X (PLLCON[2:0] = 000’b). Once again 5 MC
cycles are required to transfer the pixel data, and the WR*
(PCLK) will be 50% duty cycle. The applied CLK and
PLLCON should be selected such that is creates a 6X
multiple on MC to ensure a 50% duty cycle.
QVGA Example - For a QVGA display (320 by 240), with 16
bits of color depth and 60 frames per second, a net band-
width requirement is 73.728 Mbps. Maximum transfer rate
for the LM2502 chipset is 245 Mbps (307 Mbps raw - in-
cludes overhead), thus there is adequate bandwidth for this
application and even larger resolution displays.
20093301
FIGURE 19. Display Interface Application
20093322
FIGURE 20. RGB565 Application
L
www.national.com
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LM2502SM | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM2502SQ | Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM251 | CYAN LAMP LED |
| LM2567 | LAN DC/DC Converter |
| LM2567M | LAN DC/DC Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM2502SM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM2502SM/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| LM2502SMX/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| LM2502SQ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer |
| LM2502SQ/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
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